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GET /api/1.1/patches/2221179/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2221179,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2221179/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407222208.271838-14-pierrick.bouvier@linaro.org/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260407222208.271838-14-pierrick.bouvier@linaro.org>",
    "date": "2026-04-07T22:22:00",
    "name": "[v11,13/21] target/arm/tcg/translate.c: extract aarch64_translate_code()",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "76c917bb08a35a2c1252d4ae6da796afbba7c2fc",
    "submitter": {
        "id": 85798,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/85798/?format=api",
        "name": "Pierrick Bouvier",
        "email": "pierrick.bouvier@linaro.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407222208.271838-14-pierrick.bouvier@linaro.org/mbox/",
    "series": [
        {
            "id": 499177,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/499177/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499177",
            "date": "2026-04-07T22:21:55",
            "name": "target/arm: single-binary",
            "version": 11,
            "mbox": "http://patchwork.ozlabs.org/series/499177/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2221179/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2221179/checks/",
    "tags": {},
    "headers": {
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        "X-Received": "by 2002:a17:903:3b8f:b0:2b0:445a:8c7b with SMTP id\n d9443c01a7336-2b28181f77amr196965195ad.15.1775600549042;\n Tue, 07 Apr 2026 15:22:29 -0700 (PDT)",
        "From": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
        "To": "qemu-devel@nongnu.org",
        "Cc": "philmd@linaro.org, jim.macarthur@linaro.org,\n Paolo Bonzini <pbonzini@redhat.com>,\n Richard Henderson <richard.henderson@linaro.org>, qemu-arm@nongnu.org,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Peter Maydell <peter.maydell@linaro.org>",
        "Subject": "[PATCH v11 13/21] target/arm/tcg/translate.c: extract\n aarch64_translate_code()",
        "Date": "Tue,  7 Apr 2026 15:22:00 -0700",
        "Message-ID": "<20260407222208.271838-14-pierrick.bouvier@linaro.org>",
        "X-Mailer": "git-send-email 2.47.3",
        "In-Reply-To": "<20260407222208.271838-1-pierrick.bouvier@linaro.org>",
        "References": "<20260407222208.271838-1-pierrick.bouvier@linaro.org>",
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        "List-Id": "qemu development <qemu-devel.nongnu.org>",
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        "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"
    },
    "content": "This allows to get rid of TARGET_AARCH64, and helps with next patch\nwhich will define at runtime tcg address type, by adding a second entry\npoint in a different source file.\n\nSuggested-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nSigned-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>\n---\n target/arm/internals.h         |  2 ++\n target/arm/tcg/stubs32.c       |  7 +++++++\n target/arm/tcg/translate-a64.c |  9 +++++++++\n target/arm/tcg/translate.c     | 19 +++++++++----------\n 4 files changed, 27 insertions(+), 10 deletions(-)",
    "diff": "diff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 8ec27508473..2850edcb198 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -381,6 +381,8 @@ void arm_init_cpreg_list(ARMCPU *cpu);\n \n void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);\n void arm_translate_init(void);\n+void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,\n+                            int *max_insns, vaddr pc, void *host_pc);\n void arm_translate_code(CPUState *cs, TranslationBlock *tb,\n                         int *max_insns, vaddr pc, void *host_pc);\n \ndiff --git a/target/arm/tcg/stubs32.c b/target/arm/tcg/stubs32.c\nindex c5a0bc61f47..3945dc49e5e 100644\n--- a/target/arm/tcg/stubs32.c\n+++ b/target/arm/tcg/stubs32.c\n@@ -3,6 +3,7 @@\n  */\n \n #include \"qemu/osdep.h\"\n+#include \"target/arm/internals.h\"\n #include \"target/arm/tcg/translate.h\"\n \n \n@@ -15,3 +16,9 @@ void a64_translate_init(void)\n {\n     /* Don't initialize for 32 bits. Call site will be fixed later. */\n }\n+\n+void aarch64_translate_code(CPUState *cs, TranslationBlock *tb,\n+                            int *max_insns, vaddr pc, void *host_pc)\n+{\n+    g_assert_not_reached();\n+}\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 35ad7530c4b..7533a4d01b6 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -18,6 +18,7 @@\n  */\n #include \"qemu/osdep.h\"\n #include \"exec/target_page.h\"\n+#include \"exec/translator.h\"\n #include \"helper-a64.h\"\n #include \"helper-sme.h\"\n #include \"helper-sve.h\"\n@@ -10949,3 +10950,11 @@ const TranslatorOps aarch64_translator_ops = {\n     .translate_insn     = aarch64_tr_translate_insn,\n     .tb_stop            = aarch64_tr_tb_stop,\n };\n+\n+void aarch64_translate_code(CPUState *cpu, TranslationBlock *tb,\n+                            int *max_insns, vaddr pc, void *host_pc)\n+{\n+     DisasContext dc = {};\n+     translator_loop(cpu, tb, max_insns, pc, host_pc,\n+                     &aarch64_translator_ops, &dc.base);\n+}\ndiff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex 204f9657993..9ab926b118e 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -28,6 +28,7 @@\n #include \"semihosting/semihost.h\"\n #include \"cpregs.h\"\n #include \"exec/target_page.h\"\n+#include \"exec/translator.h\"\n #include \"helper.h\"\n #include \"helper-mve.h\"\n \n@@ -6878,18 +6879,16 @@ static const TranslatorOps thumb_translator_ops = {\n void arm_translate_code(CPUState *cpu, TranslationBlock *tb,\n                         int *max_insns, vaddr pc, void *host_pc)\n {\n-    DisasContext dc = { };\n-    const TranslatorOps *ops = &arm_translator_ops;\n     CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);\n \n-    if (EX_TBFLAG_AM32(tb_flags, THUMB)) {\n-        ops = &thumb_translator_ops;\n-    }\n-#ifdef TARGET_AARCH64\n     if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) {\n-        ops = &aarch64_translator_ops;\n+        aarch64_translate_code(cpu, tb, max_insns, pc, host_pc);\n+    } else {\n+        DisasContext dc = { };\n+        translator_loop(cpu, tb, max_insns, pc, host_pc,\n+                        (EX_TBFLAG_AM32(tb_flags, THUMB)\n+                        ? &thumb_translator_ops\n+                        : &arm_translator_ops),\n+                        &dc.base);\n     }\n-#endif\n-\n-    translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base);\n }\n",
    "prefixes": [
        "v11",
        "13/21"
    ]
}