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GET /api/1.1/patches/2221109/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2221109,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2221109/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407222208.271838-17-pierrick.bouvier@linaro.org/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260407222208.271838-17-pierrick.bouvier@linaro.org>",
    "date": "2026-04-07T22:22:03",
    "name": "[v11,16/21] target/arm/tcg/translate-a64.c: use translator_ldl_end instead of arm_ldl_code",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "9d04d37535c006cd91710b7d9ce569350d9368c7",
    "submitter": {
        "id": 85798,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/85798/?format=api",
        "name": "Pierrick Bouvier",
        "email": "pierrick.bouvier@linaro.org"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407222208.271838-17-pierrick.bouvier@linaro.org/mbox/",
    "series": [
        {
            "id": 499177,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/499177/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499177",
            "date": "2026-04-07T22:21:55",
            "name": "target/arm: single-binary",
            "version": 11,
            "mbox": "http://patchwork.ozlabs.org/series/499177/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2221109/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2221109/checks/",
    "tags": {},
    "headers": {
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        "From": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
        "To": "qemu-devel@nongnu.org",
        "Cc": "philmd@linaro.org, jim.macarthur@linaro.org,\n Paolo Bonzini <pbonzini@redhat.com>,\n Richard Henderson <richard.henderson@linaro.org>, qemu-arm@nongnu.org,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>,\n Peter Maydell <peter.maydell@linaro.org>",
        "Subject": "[PATCH v11 16/21] target/arm/tcg/translate-a64.c: use\n translator_ldl_end instead of arm_ldl_code",
        "Date": "Tue,  7 Apr 2026 15:22:03 -0700",
        "Message-ID": "<20260407222208.271838-17-pierrick.bouvier@linaro.org>",
        "X-Mailer": "git-send-email 2.47.3",
        "In-Reply-To": "<20260407222208.271838-1-pierrick.bouvier@linaro.org>",
        "References": "<20260407222208.271838-1-pierrick.bouvier@linaro.org>",
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    },
    "content": "Allows to reduce scope of target/arm/tcg/arm_ldst.h to aarch32 only.\n\nSuggested-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nSigned-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>\n---\n target/arm/tcg/translate-a64.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)",
    "diff": "diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex df2cbd66b38..48b5c572555 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -26,7 +26,6 @@\n #include \"translate-a64.h\"\n #include \"tcg/tcg-op.h\"\n #include \"qemu/log.h\"\n-#include \"arm_ldst.h\"\n #include \"semihosting/semihost.h\"\n #include \"cpregs.h\"\n \n@@ -10801,7 +10800,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n     if (pc & 3) {\n         /*\n          * PC alignment fault.  This has priority over the instruction abort\n-         * that we would receive from a translation fault via arm_ldl_code.\n+         * that we would receive from a translation fault via translator_ldl_end.\n          * This should only be possible after an indirect branch, at the\n          * start of the TB.\n          */\n@@ -10813,7 +10812,8 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n     }\n \n     s->pc_curr = pc;\n-    insn = arm_ldl_code(env, &s->base, pc, s->sctlr_b);\n+    /* Code is always little-endian on Aarch64 */\n+    insn = translator_ldl_end(env, &s->base, pc, MO_LE);\n     s->insn = insn;\n     s->base.pc_next = pc + 4;\n \n",
    "prefixes": [
        "v11",
        "16/21"
    ]
}