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GET /api/1.1/patches/2221080/?format=api
{ "id": 2221080, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2221080/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260408-jk-even-more-e825c-fixes-v1-3-b959da91a81f@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/1.1/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260408-jk-even-more-e825c-fixes-v1-3-b959da91a81f@intel.com>", "date": "2026-04-08T18:46:33", "name": "[iwl-net,3/4] ice: fix ready bitmap check for non-E822 devices", "commit_ref": null, "pull_url": null, "state": "under-review", "archived": false, "hash": "244ed73750c840aa2cd53e84e459d9e137526ebc", "submitter": { "id": 9784, "url": "http://patchwork.ozlabs.org/api/1.1/people/9784/?format=api", "name": "Jacob Keller", "email": "jacob.e.keller@intel.com" }, "delegate": { "id": 109701, "url": "http://patchwork.ozlabs.org/api/1.1/users/109701/?format=api", "username": "anguy11", "first_name": "Anthony", "last_name": "Nguyen", "email": "anthony.l.nguyen@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260408-jk-even-more-e825c-fixes-v1-3-b959da91a81f@intel.com/mbox/", "series": [ { "id": 499189, "url": "http://patchwork.ozlabs.org/api/1.1/series/499189/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=499189", "date": "2026-04-08T18:46:30", "name": "ice: E825C missing PHY timestamp interrupt fixes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499189/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2221080/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221080/checks/", "tags": {}, "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=VQfTw4r4;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=140.211.166.137; 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a=\"75841384\"", "E=Sophos;i=\"6.23,168,1770624000\"; d=\"scan'208\";a=\"75841384\"", "E=Sophos;i=\"6.23,168,1770624000\"; d=\"scan'208\";a=\"230217566\"" ], "X-ExtLoop1": "1", "From": "Jacob Keller <jacob.e.keller@intel.com>", "Date": "Wed, 08 Apr 2026 11:46:33 -0700", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260408-jk-even-more-e825c-fixes-v1-3-b959da91a81f@intel.com>", "References": "<20260408-jk-even-more-e825c-fixes-v1-0-b959da91a81f@intel.com>", "In-Reply-To": "<20260408-jk-even-more-e825c-fixes-v1-0-b959da91a81f@intel.com>", "To": "Anthony Nguyen <anthony.l.nguyen@intel.com>,\n Intel Wired LAN <intel-wired-lan@lists.osuosl.org>, netdev@vger.kernel.org", "X-Mailer": "b4 0.16-dev-306a9", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=12152;\n i=jacob.e.keller@intel.com; h=from:subject:message-id;\n bh=bDCHo9Qd8tPyja99fRKRg8JbbMO0vb09ovr28Mx4LQ8=;\n b=owGbwMvMwCWWNS3WLp9f4wXjabUkhsxri/a+NPTzr/vwVbahPO6p/ab/K+64pBTOmvEt8mbWl\n 9W3lp092VHKwiDGxSArpsii4BCy8rrxhDCtN85yMHNYmUCGMHBxCsBEzq5iZLgTzcJy6Y4z+8uJ\n 64Tm3juV/Mit4xhLVXOQtGF74E9NxVJGhns+rJIWYS+vHHaf++OYuSPD/RzjY5GT/ae3b9dNav/\n fzg8A", "X-Developer-Key": "i=jacob.e.keller@intel.com; a=openpgp;\n fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8", "X-Mailman-Original-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1775674049; x=1807210049;\n h=from:date:subject:mime-version:content-transfer-encoding:\n message-id:references:in-reply-to:to:cc;\n bh=bDCHo9Qd8tPyja99fRKRg8JbbMO0vb09ovr28Mx4LQ8=;\n b=JTeTQOr86X89gp4nGkSzk8+Mk4FbijWJ+Oviv+ArKM+U53TIQzxn3Vik\n 1g+Mdjup4t1WqBkRID20gpeMttg5MK9dM3Ykw+VbQDRDbif/MxY8Fr1t3\n KgP4fRS2mR4Trl3t+FhSuZ3lCBkZ6z0saFCJtffcrgrV4b+HE36zkF9Sg\n Aje7PPHysyK1pkadW2cuY9GC41kZ3hevOBO9UlVQUtnZE3QLhXXF/dwfn\n ewYasi8iNrDnXybuLT4IcQCb0zFonDQQGdVl59zfV5DgmCm5lzo7it0Fr\n F38oWbgtT99fBjBAcr2V8SK27ibuZR/4h/3vUx8G+PxXw7NJ69Atj1fme\n w==;", "X-Mailman-Original-Authentication-Results": [ "smtp3.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com", "smtp3.osuosl.org;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.a=rsa-sha256 header.s=Intel header.b=JTeTQOr8" ], "Subject": "[Intel-wired-lan] [PATCH iwl-net 3/4] ice: fix ready bitmap check\n for non-E822 devices", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "Aleksandr Loktionov <aleksandr.loktionov@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>,\n Timothy Miskell <timothy.miskell@intel.com>", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "The E800 hardware (apart from E810) has a ready bitmap for the PHY\nindicating which timestamp slots currently have an outstanding timestamp\nwaiting to be read by software.\n\nThis bitmap is checked in multiple places using the\nice_get_phy_tx_tstamp_ready():\n\n * ice_ptp_process_tx_tstamp() calls it to determine which timestamps to\n attempt reading from the PHY\n * ice_ptp_tx_tstamps_pending() calls it in a loop at the end of the\n miscellaneous IRQ to check if new timestamps came in while the interrupt\n handler was executing.\n * ice_ptp_maybe_trigger_tx_interrupt() calls it in the auxiliary work task\n to trigger a software interrupt in the event that the hardware logic\n gets stuck.\n\nFor E82X devices, multiple PHYs share the same block, and the parameter\npassed to the ready bitmap is a block number associated with the given\nport. For E825-C devices, the PHYs have their own independent blocks and do\nnot share, so the parameter passed needs to be the port number. For E810\ndevices, the ice_get_phy_tx_tstamp_ready() always returns all 1s regardless\nof what port, since this hardware does not have a ready bitmap. Finally,\nfor E830 devices, each PF has its own ready bitmap accessible via register,\nand the block parameter is unused.\n\nThe first call correctly uses the Tx timestamp tracker block parameter to\ncheck the appropriate timestamp block. This works because the tracker is\nsetup correctly for each timestamp device type.\n\nThe second two callers behave incorrectly for all device types other than\nthe older E822 devices. They both iterate in a loop using\nICE_GET_QUAD_NUM() which is a macro only used by E822 devices. This logic\nis incorrect for devices other than the E822 devices.\n\nFor E810 the calls would always return true, causing E810 devices to always\nattempt to trigger a software interrupt even when they have no reason to.\nFor E830, this results in duplicate work as the ready bitmap is checked\nonce per number of quads. Finally, for E825-C, this results in the pending\nchecks failing to detect timestamps on ports other than the first two.\n\nFix this by introducing a new hardware API function to ice_ptp_hw.c,\nice_check_phy_tx_tstamp_ready(). This function will check if any timestamps\nare available and returns a positive value if any timestamps are pending.\nFor E810, the function always returns false, so that the re-trigger checks\nnever happen. For E830, check the ready bitmap just once. For E82x\nhardware, check each quad. Finally, for E825-C, check every port.\n\nThe interface function returns an integer to enable reporting of error code\nif the driver is unable read the ready bitmap. This enables callers to\nhandle this case properly. The previous implementation assumed that\ntimestamps are available if they failed to read the bitmap. This is\nproblematic as it could lead to continuous software IRQ triggering if the\nPHY timestamp registers somehow become inaccessible.\n\nThis change is especially important for E825-C devices, as the missing\nchecks could leave a window open where a new timestamp could arrive while\nthe existing timestamps aren't completed. As a result, the hardware\nthreshold logic would not trigger a new interrupt. Without the check, the\ntimestamp is left unhandled, and new timestamps will not cause an interrupt\nagain until the timestamp is handled. Since both the interrupt check and\nthe backup check in the auxiliary task do not function properly, the device\nmay have Tx timestamps permanently stuck failing on a given port.\n\nThe faulty checks originate from commit d938a8cca88a (\"ice: Auxbus devices\n& driver for E822 TS\") and commit 712e876371f8 (\"ice: periodically kick Tx\ntimestamp interrupt\"), however at the time of the original coding, both\nfunctions only operated on E822 hardware. This is no longer the case, and\nhasn't been since the introduction of the ETH56G PHY model in commit\n7cab44f1c35f (\"ice: Introduce ETH56G PHY model for E825C products\")\n\nFixes: 7cab44f1c35f (\"ice: Introduce ETH56G PHY model for E825C products\")\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nReviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>\n---\n drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 1 +\n drivers/net/ethernet/intel/ice/ice_ptp.c | 40 ++++------\n drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 117 ++++++++++++++++++++++++++++\n 3 files changed, 132 insertions(+), 26 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h\nindex 9d7acc7eb2ce..1b58b054f4a5 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h\n+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h\n@@ -300,6 +300,7 @@ void ice_ptp_reset_ts_memory(struct ice_hw *hw);\n int ice_ptp_init_phc(struct ice_hw *hw);\n void ice_ptp_init_hw(struct ice_hw *hw);\n int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);\n+int ice_check_phy_tx_tstamp_ready(struct ice_hw *hw);\n int ice_ptp_one_port_cmd(struct ice_hw *hw, u8 configured_port,\n \t\t\t enum ice_ptp_tmr_cmd configured_cmd);\n \ndiff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c\nindex ada42bcc4d0b..34906f972d17 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ptp.c\n+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c\n@@ -2718,7 +2718,7 @@ static bool ice_any_port_has_timestamps(struct ice_pf *pf)\n bool ice_ptp_tx_tstamps_pending(struct ice_pf *pf)\n {\n \tstruct ice_hw *hw = &pf->hw;\n-\tunsigned int i;\n+\tint ret;\n \n \t/* Check software indicator */\n \tswitch (pf->ptp.tx_interrupt_mode) {\n@@ -2739,16 +2739,15 @@ bool ice_ptp_tx_tstamps_pending(struct ice_pf *pf)\n \t}\n \n \t/* Check hardware indicator */\n-\tfor (i = 0; i < ICE_GET_QUAD_NUM(hw->ptp.num_lports); i++) {\n-\t\tu64 tstamp_ready = 0;\n-\t\tint err;\n-\n-\t\terr = ice_get_phy_tx_tstamp_ready(&pf->hw, i, &tstamp_ready);\n-\t\tif (err || tstamp_ready)\n-\t\t\treturn true;\n+\tret = ice_check_phy_tx_tstamp_ready(hw);\n+\tif (ret < 0) {\n+\t\tdev_dbg(ice_pf_to_dev(pf), \"Unable to read PHY Tx timestamp ready bitmap, err %d\\n\",\n+\t\t\tret);\n+\t\t/* Stop triggering IRQs if we're unable to read PHY */\n+\t\treturn false;\n \t}\n \n-\treturn false;\n+\treturn ret;\n }\n \n /**\n@@ -2832,8 +2831,7 @@ static void ice_ptp_maybe_trigger_tx_interrupt(struct ice_pf *pf)\n {\n \tstruct device *dev = ice_pf_to_dev(pf);\n \tstruct ice_hw *hw = &pf->hw;\n-\tbool trigger_oicr = false;\n-\tunsigned int i;\n+\tint ret;\n \n \tif (!pf->ptp.port.tx.has_ready_bitmap)\n \t\treturn;\n@@ -2841,21 +2839,11 @@ static void ice_ptp_maybe_trigger_tx_interrupt(struct ice_pf *pf)\n \tif (!ice_pf_src_tmr_owned(pf))\n \t\treturn;\n \n-\tfor (i = 0; i < ICE_GET_QUAD_NUM(hw->ptp.num_lports); i++) {\n-\t\tu64 tstamp_ready;\n-\t\tint err;\n-\n-\t\terr = ice_get_phy_tx_tstamp_ready(&pf->hw, i, &tstamp_ready);\n-\t\tif (!err && tstamp_ready) {\n-\t\t\ttrigger_oicr = true;\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tif (trigger_oicr) {\n-\t\t/* Trigger a software interrupt, to ensure this data\n-\t\t * gets processed.\n-\t\t */\n+\tret = ice_check_phy_tx_tstamp_ready(hw);\n+\tif (ret < 0) {\n+\t\tdev_dbg(dev, \"PTP periodic task unable to read PHY timestamp ready bitmap, err %d\\n\",\n+\t\t\tret);\n+\t} else if (ret) {\n \t\tdev_dbg(dev, \"PTP periodic task detected waiting timestamps. Triggering Tx timestamp interrupt now.\\n\");\n \n \t\twr32(hw, PFINT_OICR, PFINT_OICR_TSYN_TX_M);\ndiff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\nindex 441b5f10e4bb..64ad5ed5c688 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n+++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c\n@@ -2168,6 +2168,35 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port)\n \treturn 0;\n }\n \n+/**\n+ * ice_check_phy_tx_tstamp_ready_eth56g - Check Tx memory status for all ports\n+ * @hw: pointer to the HW struct\n+ *\n+ * Check the PHY_REG_TX_MEMORY_STATUS for all ports. A set bit indicates\n+ * a waiting timestamp.\n+ *\n+ * Return: 1 if any port has at least one timestamp ready bit set,\n+ * 0 otherwise, and a negative error code if unable to read the bitmap.\n+ */\n+static int ice_check_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw)\n+{\n+\tint port;\n+\n+\tfor (port = 0; port < hw->ptp.num_lports; port++) {\n+\t\tu64 tstamp_ready;\n+\t\tint err;\n+\n+\t\terr = ice_get_phy_tx_tstamp_ready(hw, port, &tstamp_ready);\n+\t\tif (err)\n+\t\t\treturn err;\n+\n+\t\tif (tstamp_ready)\n+\t\t\treturn 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /**\n * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status\n * @hw: pointer to the HW struct\n@@ -4318,6 +4347,35 @@ ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)\n \treturn 0;\n }\n \n+/**\n+ * ice_check_phy_tx_tstamp_ready_e82x - Check Tx memory status for all quads\n+ * @hw: pointer to the HW struct\n+ *\n+ * Check the Q_REG_TX_MEMORY_STATUS for all quads. A set bit indicates\n+ * a waiting timestamp.\n+ *\n+ * Return: 1 if any quad has at least one timestamp ready bit set,\n+ * 0 otherwise, and a negative error value if unable to read the bitmap.\n+ */\n+static int ice_check_phy_tx_tstamp_ready_e82x(struct ice_hw *hw)\n+{\n+\tint quad;\n+\n+\tfor (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) {\n+\t\tu64 tstamp_ready;\n+\t\tint err;\n+\n+\t\terr = ice_get_phy_tx_tstamp_ready(hw, quad, &tstamp_ready);\n+\t\tif (err)\n+\t\t\treturn err;\n+\n+\t\tif (tstamp_ready)\n+\t\t\treturn 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /**\n * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt\n * @hw: pointer to the HW struct\n@@ -4870,6 +4928,23 @@ ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready)\n \treturn 0;\n }\n \n+/**\n+ * ice_check_phy_tx_tstamp_ready_e810 - Check Tx memory status register\n+ * @hw: pointer to the HW struct\n+ *\n+ * The E810 devices do not have a Tx memory status register. Note this is\n+ * intentionally different behavior from ice_get_phy_tx_tstamp_ready_e810\n+ * which always says that all bits are ready. This function is called in cases\n+ * where code will trigger interrupts if timestamps are waiting, and should\n+ * not be called for E810 hardware.\n+ *\n+ * Return: 0.\n+ */\n+static int ice_check_phy_tx_tstamp_ready_e810(struct ice_hw *hw)\n+{\n+\treturn 0;\n+}\n+\n /* E810 SMA functions\n *\n * The following functions operate specifically on E810 hardware and are used\n@@ -5124,6 +5199,21 @@ static void ice_get_phy_tx_tstamp_ready_e830(const struct ice_hw *hw, u8 port,\n \t*tstamp_ready |= rd32(hw, E830_PRTMAC_TS_TX_MEM_VALID_L);\n }\n \n+/**\n+ * ice_check_phy_tx_tstamp_ready_e830 - Check Tx memory status register\n+ * @hw: pointer to the HW struct\n+ *\n+ * Return: 1 if the device has waiting timestamps, 0 otherwise.\n+ */\n+static int ice_check_phy_tx_tstamp_ready_e830(struct ice_hw *hw)\n+{\n+\tu64 tstamp_ready;\n+\n+\tice_get_phy_tx_tstamp_ready_e830(hw, 0, &tstamp_ready);\n+\n+\treturn !!tstamp_ready;\n+}\n+\n /**\n * ice_ptp_init_phy_e830 - initialize PHY parameters\n * @ptp: pointer to the PTP HW struct\n@@ -5716,6 +5806,33 @@ int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)\n \t}\n }\n \n+/**\n+ * ice_check_phy_tx_tstamp_ready - Check PHY Tx timestamp memory status\n+ * @hw: pointer to the HW struct\n+ *\n+ * Check the PHY for Tx timestamp memory status on all ports. If you need to\n+ * see individual timestamp status for each index, use\n+ * ice_get_phy_tx_tstamp_ready() instead.\n+ *\n+ * Return: 1 if any port has timestamps available, 0 if there are no timestamps\n+ * available, and a negative error code on failure.\n+ */\n+int ice_check_phy_tx_tstamp_ready(struct ice_hw *hw)\n+{\n+\tswitch (hw->mac_type) {\n+\tcase ICE_MAC_E810:\n+\t\treturn ice_check_phy_tx_tstamp_ready_e810(hw);\n+\tcase ICE_MAC_E830:\n+\t\treturn ice_check_phy_tx_tstamp_ready_e830(hw);\n+\tcase ICE_MAC_GENERIC:\n+\t\treturn ice_check_phy_tx_tstamp_ready_e82x(hw);\n+\tcase ICE_MAC_GENERIC_3K_E825:\n+\t\treturn ice_check_phy_tx_tstamp_ready_eth56g(hw);\n+\tdefault:\n+\t\treturn -EOPNOTSUPP;\n+\t}\n+}\n+\n /**\n * ice_cgu_get_pin_desc_e823 - get pin description array\n * @hw: pointer to the hw struct\n", "prefixes": [ "iwl-net", "3/4" ] }