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{ "id": 2220967, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220967/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260408132341.430684-1-naveen.siddegowda@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260408132341.430684-1-naveen.siddegowda@oss.qualcomm.com>", "date": "2026-04-08T13:23:41", "name": "[AArch64] : Use MOVI for low‑64‑bit integer SIMD constant vectors [PR113926]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8a964b6702111a209657ecf602d3d2d19d24d801", "submitter": { "id": 93028, "url": "http://patchwork.ozlabs.org/api/1.1/people/93028/?format=api", "name": "Naveen", "email": "naveen.siddegowda@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260408132341.430684-1-naveen.siddegowda@oss.qualcomm.com/mbox/", "series": [ { "id": 499142, "url": "http://patchwork.ozlabs.org/api/1.1/series/499142/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=499142", "date": "2026-04-08T13:23:41", "name": "[AArch64] : Use MOVI for low‑64‑bit integer SIMD constant vectors [PR113926]", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499142/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220967/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220967/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass 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<naveen.siddegowda@oss.qualcomm.com>", "To": "gcc-patches@gcc.gnu.org", "Cc": "Naveen <naveen.siddegowda@oss.qualcomm.com>", "Subject": "[PATCH] =?utf-8?q?=5BAArch64=5D=3A_Use_MOVI_for_low=E2=80=9164?=\n\t=?utf-8?q?=E2=80=91bit_integer_SIMD_constant_vectors_=5BPR113926=5D?=", "Date": "Wed, 8 Apr 2026 06:23:41 -0700", "Message-Id": "<20260408132341.430684-1-naveen.siddegowda@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-ORIG-GUID": "wVvqeGyMyJVdImtwpRnm8oCfTDcCCZ8g", "X-Proofpoint-GUID": "wVvqeGyMyJVdImtwpRnm8oCfTDcCCZ8g", "X-Authority-Analysis": "v=2.4 cv=WZs8rUhX c=1 sm=1 tr=0 ts=69d656e3 cx=c_pps\n a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=5KLPUuaC_9wA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22\n a=EUspDBNiAAAA:8 a=EnneN2EoE92wYLOZMHcA:9 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spamscore=0 priorityscore=1501 impostorscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080123", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Extend AdvSIMD constant materialization to recognize 128‑bit integer vector\nconstants where the low 64 bits contain a duplicated scalar value and the high\n64 bits are zero.\nBootstrapped and tested on aarch64-linux-gnu.\n\nPR target/113926\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64.cc (aarch64_const_vec_int_zero_p): New function.\n\t(aarch64_simd_valid_mov_imm_low64): New function.\n\ngcc/testsuite/ChangeLog:\n\t* gcc.target/aarch64/pr113926.c: New test.\n\nSigned-off-by: Naveen <naveen.siddegowda@oss.qualcomm.com>\n---\n gcc/config/aarch64/aarch64.cc | 89 ++++++++++++++++++++-\n gcc/testsuite/gcc.target/aarch64/pr113926.c | 15 ++++\n 2 files changed, 103 insertions(+), 1 deletion(-)\n create mode 100644 gcc/testsuite/gcc.target/aarch64/pr113926.c", "diff": "diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\nindex 4405074cdad..50bfb6f65bd 100644\n--- a/gcc/config/aarch64/aarch64.cc\n+++ b/gcc/config/aarch64/aarch64.cc\n@@ -24639,11 +24639,90 @@ aarch64_expand_maskloadstore (rtx *operands, machine_mode mode)\n return false;\n }\n \n+/* Return true if X is a constant integer zero. */\n+static bool\n+aarch64_const_vec_int_zero_p (rtx x)\n+{\n+ return CONST_INT_P (x) && INTVAL (x) == 0;\n+}\n+\n+/* Return true if OP is a 128-bit vector constant whose low 64 bits are all\n+ equal to the same scalar integer value and whose high 64 bits are zero. */\n+static bool\n+aarch64_simd_valid_mov_imm_low64 (rtx op, simd_immediate_info *info,\n+\t\t\t\t unsigned *out_width)\n+{\n+ if (!CONST_VECTOR_P (op))\n+ return false;\n+\n+ /* Handle 128-bit vectors. */\n+ machine_mode mode = GET_MODE (op);\n+ if (!known_eq (GET_MODE_SIZE (mode), 16))\n+ return false;\n+\n+ scalar_mode inner_mode = GET_MODE_INNER (mode);\n+ scalar_int_mode int_mode;\n+\n+ /* Vector elements must be integers. */\n+ if (!is_a <scalar_int_mode> (inner_mode, &int_mode))\n+ return false;\n+\n+ /* Elements wider than 64 bits cannot form a low-64-bit split. */\n+ if (GET_MODE_BITSIZE (int_mode) > 64)\n+ return false;\n+\n+ /* Determine the start of the low and high 64-bit halves, taking target\n+ endianness into account. */\n+ unsigned int nunits = GET_MODE_NUNITS (mode).to_constant ();\n+ unsigned int low_nunits = 64 / GET_MODE_BITSIZE (int_mode);\n+ unsigned int low_first = BYTES_BIG_ENDIAN ? nunits - low_nunits : 0;\n+ unsigned int high_first = BYTES_BIG_ENDIAN ? 0 : low_nunits;\n+\n+ rtx first = CONST_VECTOR_ELT (op, low_first);\n+\n+ /* Low half must be a duplicated integer constant. */\n+ if (!CONST_INT_P (first))\n+ return false;\n+\n+ for (unsigned int i = 0; i < low_nunits; ++i)\n+ if (!rtx_equal_p (CONST_VECTOR_ELT (op, low_first + i), first))\n+ return false;\n+\n+ for (unsigned int i = 0; i < low_nunits; ++i)\n+ if (!aarch64_const_vec_int_zero_p (CONST_VECTOR_ELT (op, high_first + i)))\n+ return false;\n+\n+ machine_mode low_mode;\n+ switch (int_mode)\n+ {\n+ case E_QImode: low_mode = V8QImode; break;\n+ case E_HImode: low_mode = V4HImode; break;\n+ case E_SImode: low_mode = V2SImode; break;\n+ default:\n+\treturn false;\n+ }\n+\n+ HOST_WIDE_INT val = INTVAL (first);\n+ rtx low_vec = aarch64_simd_gen_const_vector_dup (low_mode, val);\n+ simd_immediate_info tmp;\n+\n+ /* Validate whether the low 64-bit vector can be encoded as a MOV immediate. */\n+ if (!aarch64_simd_valid_imm (low_vec, &tmp, AARCH64_CHECK_MOV))\n+ return false;\n+\n+ if (info)\n+ *info = tmp;\n+ if (out_width)\n+ *out_width = 64;\n+ return true;\n+}\n+\n /* Return true if OP is a valid SIMD move immediate for SVE or AdvSIMD. */\n bool\n aarch64_simd_valid_mov_imm (rtx op)\n {\n- return aarch64_simd_valid_imm (op, NULL, AARCH64_CHECK_MOV);\n+ return (aarch64_simd_valid_imm (op, NULL, AARCH64_CHECK_MOV)\n+\t || aarch64_simd_valid_mov_imm_low64 (op, NULL, NULL));\n }\n \n /* Return true if OP is a valid SIMD orr immediate for SVE or AdvSIMD. */\n@@ -26966,10 +27045,18 @@ aarch64_output_simd_imm (rtx const_vector, unsigned width,\n char element_char;\n \n struct simd_immediate_info info;\n+ unsigned output_width = width;\n \n is_valid = aarch64_simd_valid_imm (const_vector, &info, which);\n+\n+ if (!is_valid && which == AARCH64_CHECK_MOV)\n+ is_valid = aarch64_simd_valid_mov_imm_low64 (const_vector, &info,\n+\t\t\t\t\t\t &output_width);\n+\n gcc_assert (is_valid);\n \n+ width = output_width;\n+\n element_char = sizetochar (GET_MODE_BITSIZE (info.elt_mode));\n lane_count = width / GET_MODE_BITSIZE (info.elt_mode);\n \ndiff --git a/gcc/testsuite/gcc.target/aarch64/pr113926.c b/gcc/testsuite/gcc.target/aarch64/pr113926.c\nnew file mode 100644\nindex 00000000000..bc7cff8ada1\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/aarch64/pr113926.c\n@@ -0,0 +1,15 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2\" } */\n+/* { dg-additional-options \"-march=armv8-a+fp16\" } */\n+\n+typedef int vect128_int __attribute__((vector_size(16)));\n+\n+vect128_int\n+f1 (void)\n+{\n+ return (vect128_int){1, 1, 0, 0};\n+}\n+\n+/* Should use MOVI instruction. */\n+/* { dg-final { scan-assembler-times {\\tmovi\\tv[0-9]+\\.2s, 0x1} 1 } } */\n+/* { dg-final { scan-assembler-not {\\tldr\\tq[0-9]+,} } } */\n", "prefixes": [ "AArch64" ] }