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GET /api/1.1/patches/2220943/?format=api
{ "id": 2220943, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220943/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260408091136.2794546-5-varadarajan.narayanan@oss.qualcomm.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260408091136.2794546-5-varadarajan.narayanan@oss.qualcomm.com>", "date": "2026-04-08T09:11:31", "name": "[v1,4/9] pinctrl: qcom: Add ipq5210 pinctrl driver", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "2dc4c4d714111cca63bd3470e0245c5c43e06229", "submitter": { "id": 92283, "url": "http://patchwork.ozlabs.org/api/1.1/people/92283/?format=api", "name": "Varadarajan Narayanan", "email": "varadarajan.narayanan@oss.qualcomm.com" }, "delegate": { "id": 151538, "url": "http://patchwork.ozlabs.org/api/1.1/users/151538/?format=api", "username": "kcxt", "first_name": "Casey", "last_name": "Connolly", "email": "casey.connolly@linaro.org" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260408091136.2794546-5-varadarajan.narayanan@oss.qualcomm.com/mbox/", "series": [ { "id": 499137, "url": "http://patchwork.ozlabs.org/api/1.1/series/499137/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=499137", "date": "2026-04-08T09:11:27", "name": "Qualcomm IPQ5210 SoC bringup", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499137/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220943/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220943/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=WqBFxIYO;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=ROx57fKM;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=oss.qualcomm.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"WqBFxIYO\";\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"ROx57fKM\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=none (p=none dis=none)\n header.from=oss.qualcomm.com", "phobos.denx.de; spf=pass\n smtp.mailfrom=varadarajan.narayanan@oss.qualcomm.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frNNq0ZF8z1yD3\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 08 Apr 2026 22:56:27 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 9D7DE8419E;\n\tWed, 8 Apr 2026 14:55:32 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 6C623838BB; Wed, 8 Apr 2026 11:12:41 +0200 (CEST)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 02F3D80433\n for <u-boot@lists.denx.de>; Wed, 8 Apr 2026 11:12:38 +0200 (CEST)", "from pps.filterd (m0279872.ppops.net [127.0.0.1])\n by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 6387FwAH1619624\n for <u-boot@lists.denx.de>; Wed, 8 Apr 2026 09:12:36 GMT", "from mail-pl1-f199.google.com (mail-pl1-f199.google.com\n [209.85.214.199])\n by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ddacrj10w-1\n (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n for <u-boot@lists.denx.de>; Wed, 08 Apr 2026 09:12:36 +0000 (GMT)", "by mail-pl1-f199.google.com with SMTP id\n d9443c01a7336-2b258636d16so61656545ad.2\n for <u-boot@lists.denx.de>; Wed, 08 Apr 2026 02:12:35 -0700 (PDT)", "from hu-varada-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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"snlakshm@qti.qualcomm.com, gopinath.sekar@oss.qualcomm.com", "Subject": "[PATCH v1 4/9] pinctrl: qcom: Add ipq5210 pinctrl driver", "Date": "Wed, 8 Apr 2026 14:41:31 +0530", "Message-Id": "<20260408091136.2794546-5-varadarajan.narayanan@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260408091136.2794546-1-varadarajan.narayanan@oss.qualcomm.com>", "References": "<20260408091136.2794546-1-varadarajan.narayanan@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-ORIG-GUID": "MOzcSJiqiJbuMPfzpkjWkx2yiUEb8Xvc", "X-Proofpoint-GUID": "MOzcSJiqiJbuMPfzpkjWkx2yiUEb8Xvc", "X-Authority-Analysis": "v=2.4 cv=WZs8rUhX c=1 sm=1 tr=0 ts=69d61c04 cx=c_pps\n a=JL+w9abYAAE89/QcEU+0QA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8\n a=NzvCGKM8m0lGn9t9IsgA:9 a=O8hF6Hzn-FEA:10 a=324X-CrmTo6CU4MGRt3R:22", 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classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604080082", "X-Mailman-Approved-At": "Wed, 08 Apr 2026 14:55:29 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add pinctrl driver for the TLMM block found in the ipq5210 SoC.\n\nSigned-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>\n---\n drivers/pinctrl/qcom/Kconfig | 8 +\n drivers/pinctrl/qcom/Makefile | 1 +\n drivers/pinctrl/qcom/pinctrl-ipq5210.c | 349 +++++++++++++++++++++++++\n 3 files changed, 358 insertions(+)\n create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5210.c", "diff": "diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig\nindex 580308621b1..d30526b0167 100644\n--- a/drivers/pinctrl/qcom/Kconfig\n+++ b/drivers/pinctrl/qcom/Kconfig\n@@ -38,6 +38,14 @@ config PINCTRL_QCOM_IPQ4019\n \t Say Y here to enable support for pinctrl on the IPQ4019 SoC,\n \t as well as the associated GPIO driver.\n \n+config PINCTRL_QCOM_IPQ5210\n+\tbool \"Qualcomm IPQ5210 Pinctrl\"\n+\tdefault y if PINCTRL_QCOM_GENERIC\n+\tselect PINCTRL_QCOM\n+\thelp\n+\t Say Y here to enable support for pinctrl on the IPQ5210 SoC,\n+\t as well as the associated GPIO driver.\n+\n config PINCTRL_QCOM_IPQ5424\n \tbool \"Qualcomm IPQ5424 Pinctrl\"\n \tdefault y if PINCTRL_QCOM_GENERIC\ndiff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile\nindex b5a111605ed..34ae56bb007 100644\n--- a/drivers/pinctrl/qcom/Makefile\n+++ b/drivers/pinctrl/qcom/Makefile\n@@ -5,6 +5,7 @@\n obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o\n obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o\n obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o\n+obj-$(CONFIG_PINCTRL_QCOM_IPQ5210) += pinctrl-ipq5210.o\n obj-$(CONFIG_PINCTRL_QCOM_IPQ5424) += pinctrl-ipq5424.o\n obj-$(CONFIG_PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o\n obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o\ndiff --git a/drivers/pinctrl/qcom/pinctrl-ipq5210.c b/drivers/pinctrl/qcom/pinctrl-ipq5210.c\nnew file mode 100644\nindex 00000000000..2baff884bf3\n--- /dev/null\n+++ b/drivers/pinctrl/qcom/pinctrl-ipq5210.c\n@@ -0,0 +1,349 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Qualcomm IPQ5210 pinctrl\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ */\n+\n+#include <dm.h>\n+\n+#include \"pinctrl-qcom.h\"\n+\n+#define MAX_PIN_NAME_LEN 32\n+static char pin_name[MAX_PIN_NAME_LEN] __section(\".data\");\n+\n+enum ipq5210_functions {\n+\tmsm_mux_atest_char_start,\n+\tmsm_mux_atest_char_status0,\n+\tmsm_mux_atest_char_status1,\n+\tmsm_mux_atest_char_status2,\n+\tmsm_mux_atest_char_status3,\n+\tmsm_mux_atest_tic_en,\n+\tmsm_mux_audio_pri,\n+\tmsm_mux_audio_pri_mclk_out0,\n+\tmsm_mux_audio_pri_mclk_in0,\n+\tmsm_mux_audio_pri_mclk_out1,\n+\tmsm_mux_audio_pri_mclk_in1,\n+\tmsm_mux_audio_pri_mclk_out2,\n+\tmsm_mux_audio_pri_mclk_in2,\n+\tmsm_mux_audio_pri_mclk_out3,\n+\tmsm_mux_audio_pri_mclk_in3,\n+\tmsm_mux_audio_sec,\n+\tmsm_mux_audio_sec_mclk_out0,\n+\tmsm_mux_audio_sec_mclk_in0,\n+\tmsm_mux_audio_sec_mclk_out1,\n+\tmsm_mux_audio_sec_mclk_in1,\n+\tmsm_mux_audio_sec_mclk_out2,\n+\tmsm_mux_audio_sec_mclk_in2,\n+\tmsm_mux_audio_sec_mclk_out3,\n+\tmsm_mux_audio_sec_mclk_in3,\n+\tmsm_mux_core_voltage_0,\n+\tmsm_mux_cri_trng0,\n+\tmsm_mux_cri_trng1,\n+\tmsm_mux_cri_trng2,\n+\tmsm_mux_cri_trng3,\n+\tmsm_mux_dbg_out_clk,\n+\tmsm_mux_dg_out,\n+\tmsm_mux_gcc_plltest_bypassnl,\n+\tmsm_mux_gcc_plltest_resetn,\n+\tmsm_mux_gcc_tlmm,\n+\tmsm_mux_gpio,\n+\tmsm_mux_led0,\n+\tmsm_mux_led1,\n+\tmsm_mux_led2,\n+\tmsm_mux_mdc_mst,\n+\tmsm_mux_mdc_slv0,\n+\tmsm_mux_mdc_slv1,\n+\tmsm_mux_mdc_slv2,\n+\tmsm_mux_mdio_mst,\n+\tmsm_mux_mdio_slv0,\n+\tmsm_mux_mdio_slv1,\n+\tmsm_mux_mdio_slv2,\n+\tmsm_mux_mux_tod_out,\n+\tmsm_mux_pcie0_clk_req_n,\n+\tmsm_mux_pcie0_wake,\n+\tmsm_mux_pcie1_clk_req_n,\n+\tmsm_mux_pcie1_wake,\n+\tmsm_mux_pll_test,\n+\tmsm_mux_pon_active_led,\n+\tmsm_mux_pon_mux_sel,\n+\tmsm_mux_pon_rx,\n+\tmsm_mux_pon_rx_los,\n+\tmsm_mux_pon_tx,\n+\tmsm_mux_pon_tx_burst,\n+\tmsm_mux_pon_tx_dis,\n+\tmsm_mux_pon_tx_fault,\n+\tmsm_mux_pon_tx_sd,\n+\tmsm_mux_gpn_rx_los,\n+\tmsm_mux_gpn_tx_burst,\n+\tmsm_mux_gpn_tx_dis,\n+\tmsm_mux_gpn_tx_fault,\n+\tmsm_mux_gpn_tx_sd,\n+\tmsm_mux_pps,\n+\tmsm_mux_pwm0,\n+\tmsm_mux_pwm1,\n+\tmsm_mux_pwm2,\n+\tmsm_mux_pwm3,\n+\tmsm_mux_qdss_cti_trig_in_a0,\n+\tmsm_mux_qdss_cti_trig_in_a1,\n+\tmsm_mux_qdss_cti_trig_in_b0,\n+\tmsm_mux_qdss_cti_trig_in_b1,\n+\tmsm_mux_qdss_cti_trig_out_a0,\n+\tmsm_mux_qdss_cti_trig_out_a1,\n+\tmsm_mux_qdss_cti_trig_out_b0,\n+\tmsm_mux_qdss_cti_trig_out_b1,\n+\tmsm_mux_qdss_traceclk_a,\n+\tmsm_mux_qdss_tracectl_a,\n+\tmsm_mux_qdss_tracedata_a,\n+\tmsm_mux_qrng_rosc0,\n+\tmsm_mux_qrng_rosc1,\n+\tmsm_mux_qrng_rosc2,\n+\tmsm_mux_qspi_data,\n+\tmsm_mux_qspi_clk,\n+\tmsm_mux_qspi_cs_n,\n+\tmsm_mux_qup_se0,\n+\tmsm_mux_qup_se1,\n+\tmsm_mux_qup_se2,\n+\tmsm_mux_qup_se3,\n+\tmsm_mux_qup_se4,\n+\tmsm_mux_qup_se5,\n+\tmsm_mux_qup_se5_l1,\n+\tmsm_mux_resout,\n+\tmsm_mux_rx_los0,\n+\tmsm_mux_rx_los1,\n+\tmsm_mux_rx_los2,\n+\tmsm_mux_sdc_clk,\n+\tmsm_mux_sdc_cmd,\n+\tmsm_mux_sdc_data,\n+\tmsm_mux_tsens_max,\n+\tmsm_mux__,\n+};\n+\n+#define MSM_PIN_FUNCTION(fname)\t\t\t\t\\\n+\t[msm_mux_##fname] = {#fname, msm_mux_##fname}\n+\n+static const struct pinctrl_function msm_pinctrl_functions[] = {\n+\tMSM_PIN_FUNCTION(atest_char_start),\n+\tMSM_PIN_FUNCTION(atest_char_status0),\n+\tMSM_PIN_FUNCTION(atest_char_status1),\n+\tMSM_PIN_FUNCTION(atest_char_status2),\n+\tMSM_PIN_FUNCTION(atest_char_status3),\n+\tMSM_PIN_FUNCTION(atest_tic_en),\n+\tMSM_PIN_FUNCTION(audio_pri),\n+\tMSM_PIN_FUNCTION(audio_pri_mclk_out0),\n+\tMSM_PIN_FUNCTION(audio_pri_mclk_in0),\n+\tMSM_PIN_FUNCTION(audio_pri_mclk_out1),\n+\tMSM_PIN_FUNCTION(audio_pri_mclk_in1),\n+\tMSM_PIN_FUNCTION(audio_pri_mclk_out2),\n+\tMSM_PIN_FUNCTION(audio_pri_mclk_in2),\n+\tMSM_PIN_FUNCTION(audio_pri_mclk_out3),\n+\tMSM_PIN_FUNCTION(audio_pri_mclk_in3),\n+\tMSM_PIN_FUNCTION(audio_sec),\n+\tMSM_PIN_FUNCTION(audio_sec_mclk_out0),\n+\tMSM_PIN_FUNCTION(audio_sec_mclk_in0),\n+\tMSM_PIN_FUNCTION(audio_sec_mclk_out1),\n+\tMSM_PIN_FUNCTION(audio_sec_mclk_in1),\n+\tMSM_PIN_FUNCTION(audio_sec_mclk_out2),\n+\tMSM_PIN_FUNCTION(audio_sec_mclk_in2),\n+\tMSM_PIN_FUNCTION(audio_sec_mclk_out3),\n+\tMSM_PIN_FUNCTION(audio_sec_mclk_in3),\n+\tMSM_PIN_FUNCTION(core_voltage_0),\n+\tMSM_PIN_FUNCTION(cri_trng0),\n+\tMSM_PIN_FUNCTION(cri_trng1),\n+\tMSM_PIN_FUNCTION(cri_trng2),\n+\tMSM_PIN_FUNCTION(cri_trng3),\n+\tMSM_PIN_FUNCTION(dbg_out_clk),\n+\tMSM_PIN_FUNCTION(dg_out),\n+\tMSM_PIN_FUNCTION(gcc_plltest_bypassnl),\n+\tMSM_PIN_FUNCTION(gcc_plltest_resetn),\n+\tMSM_PIN_FUNCTION(gcc_tlmm),\n+\tMSM_PIN_FUNCTION(gpio),\n+\tMSM_PIN_FUNCTION(led0),\n+\tMSM_PIN_FUNCTION(led1),\n+\tMSM_PIN_FUNCTION(led2),\n+\tMSM_PIN_FUNCTION(mdc_mst),\n+\tMSM_PIN_FUNCTION(mdc_slv0),\n+\tMSM_PIN_FUNCTION(mdc_slv1),\n+\tMSM_PIN_FUNCTION(mdc_slv2),\n+\tMSM_PIN_FUNCTION(mdio_mst),\n+\tMSM_PIN_FUNCTION(mdio_slv0),\n+\tMSM_PIN_FUNCTION(mdio_slv1),\n+\tMSM_PIN_FUNCTION(mdio_slv2),\n+\tMSM_PIN_FUNCTION(mux_tod_out),\n+\tMSM_PIN_FUNCTION(pcie0_clk_req_n),\n+\tMSM_PIN_FUNCTION(pcie0_wake),\n+\tMSM_PIN_FUNCTION(pcie1_clk_req_n),\n+\tMSM_PIN_FUNCTION(pcie1_wake),\n+\tMSM_PIN_FUNCTION(pll_test),\n+\tMSM_PIN_FUNCTION(pon_active_led),\n+\tMSM_PIN_FUNCTION(pon_mux_sel),\n+\tMSM_PIN_FUNCTION(pon_rx),\n+\tMSM_PIN_FUNCTION(pon_rx_los),\n+\tMSM_PIN_FUNCTION(pon_tx),\n+\tMSM_PIN_FUNCTION(pon_tx_burst),\n+\tMSM_PIN_FUNCTION(pon_tx_dis),\n+\tMSM_PIN_FUNCTION(pon_tx_fault),\n+\tMSM_PIN_FUNCTION(pon_tx_sd),\n+\tMSM_PIN_FUNCTION(gpn_rx_los),\n+\tMSM_PIN_FUNCTION(gpn_tx_burst),\n+\tMSM_PIN_FUNCTION(gpn_tx_dis),\n+\tMSM_PIN_FUNCTION(gpn_tx_fault),\n+\tMSM_PIN_FUNCTION(gpn_tx_sd),\n+\tMSM_PIN_FUNCTION(pps),\n+\tMSM_PIN_FUNCTION(pwm0),\n+\tMSM_PIN_FUNCTION(pwm1),\n+\tMSM_PIN_FUNCTION(pwm2),\n+\tMSM_PIN_FUNCTION(pwm3),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_in_a0),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_in_a1),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_in_b0),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_in_b1),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_out_a0),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_out_a1),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_out_b0),\n+\tMSM_PIN_FUNCTION(qdss_cti_trig_out_b1),\n+\tMSM_PIN_FUNCTION(qdss_traceclk_a),\n+\tMSM_PIN_FUNCTION(qdss_tracectl_a),\n+\tMSM_PIN_FUNCTION(qdss_tracedata_a),\n+\tMSM_PIN_FUNCTION(qrng_rosc0),\n+\tMSM_PIN_FUNCTION(qrng_rosc1),\n+\tMSM_PIN_FUNCTION(qrng_rosc2),\n+\tMSM_PIN_FUNCTION(qspi_data),\n+\tMSM_PIN_FUNCTION(qspi_clk),\n+\tMSM_PIN_FUNCTION(qspi_cs_n),\n+\tMSM_PIN_FUNCTION(qup_se0),\n+\tMSM_PIN_FUNCTION(qup_se1),\n+\tMSM_PIN_FUNCTION(qup_se2),\n+\tMSM_PIN_FUNCTION(qup_se3),\n+\tMSM_PIN_FUNCTION(qup_se4),\n+\tMSM_PIN_FUNCTION(qup_se5),\n+\tMSM_PIN_FUNCTION(qup_se5_l1),\n+\tMSM_PIN_FUNCTION(resout),\n+\tMSM_PIN_FUNCTION(rx_los0),\n+\tMSM_PIN_FUNCTION(rx_los1),\n+\tMSM_PIN_FUNCTION(rx_los2),\n+\tMSM_PIN_FUNCTION(sdc_clk),\n+\tMSM_PIN_FUNCTION(sdc_cmd),\n+\tMSM_PIN_FUNCTION(sdc_data),\n+\tMSM_PIN_FUNCTION(tsens_max),\n+};\n+\n+typedef unsigned int msm_pin_function[10];\n+\n+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \\\n+\t[id] = { msm_mux_gpio, /* gpio mode */\t\\\n+\t\t\tmsm_mux_##f1,\t\t\t\\\n+\t\t\tmsm_mux_##f2,\t\t\t\\\n+\t\t\tmsm_mux_##f3,\t\t\t\\\n+\t\t\tmsm_mux_##f4,\t\t\t\\\n+\t\t\tmsm_mux_##f5,\t\t\t\\\n+\t\t\tmsm_mux_##f6,\t\t\t\\\n+\t\t\tmsm_mux_##f7,\t\t\t\\\n+\t\t\tmsm_mux_##f8,\t\t\t\\\n+\t\t\tmsm_mux_##f9,\t\t\t\\\n+\t}\n+\n+static const msm_pin_function ipq5210_pin_functions[] = {\n+\tPINGROUP(0, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),\n+\tPINGROUP(1, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),\n+\tPINGROUP(2, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),\n+\tPINGROUP(3, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),\n+\tPINGROUP(4, sdc_cmd, qspi_cs_n, _, _, _, _, _, _, _),\n+\tPINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _),\n+\tPINGROUP(6, qup_se0, led0, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _),\n+\tPINGROUP(7, qup_se0, led1, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _),\n+\tPINGROUP(8, qup_se0, pwm1, audio_pri_mclk_out2, audio_pri_mclk_in2, _, cri_trng2, qdss_tracedata_a, _, _),\n+\tPINGROUP(9, qup_se0, led2, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _),\n+\tPINGROUP(10, pon_rx_los, qup_se3, pwm0, _, _, qdss_tracedata_a, _, _, _),\n+\tPINGROUP(11, pon_active_led, qup_se3, pwm0, _, _, qdss_tracedata_a, _, _, _),\n+\tPINGROUP(12, pon_tx_dis, qup_se2, pwm0, audio_pri_mclk_out0, audio_pri_mclk_in0, _, qrng_rosc0, qdss_tracedata_a, _),\n+\tPINGROUP(13, gpn_tx_dis, qup_se2, pwm0, audio_pri_mclk_out3, audio_pri_mclk_in3, _, qrng_rosc1, qdss_tracedata_a, _),\n+\tPINGROUP(14, pon_tx_burst, qup_se0, _, qrng_rosc2, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(15, pon_tx, qup_se0, _, qdss_tracedata_a, _, _, _, _, _),\n+\tPINGROUP(16, pon_tx_sd, audio_sec_mclk_out1, audio_sec_mclk_in1, qdss_cti_trig_out_b0, _, _, _, _, _),\n+\tPINGROUP(17, pon_tx_fault, audio_sec_mclk_out0, audio_sec_mclk_in0, _, _, _, _, _, _),\n+\tPINGROUP(18, pps, pll_test, _, _, _, _, _, _, _),\n+\tPINGROUP(19, mux_tod_out, audio_pri_mclk_out1, audio_pri_mclk_in1, _, _, _, _, _, _),\n+\tPINGROUP(20, qup_se2, mdc_slv1, tsens_max, qdss_tracedata_a, _, _, _, _, _),\n+\tPINGROUP(21, qup_se2, mdio_slv1, qdss_tracedata_a, _, _, _, _, _, _),\n+\tPINGROUP(22, core_voltage_0, qup_se3, pwm3, _, _, _, _, _, _),\n+\tPINGROUP(23, led0, qup_se3, dbg_out_clk, qdss_traceclk_a, _, _, _, _, _),\n+\tPINGROUP(24, _, _, _, _, _, _, _, _, _),\n+\tPINGROUP(25, _, _, _, _, _, _, _, _, _),\n+\tPINGROUP(26, mdc_mst, led2, _, qdss_tracectl_a, _, _, _, _, _),\n+\tPINGROUP(27, mdio_mst, led1, _, _, _, _, _, _, _),\n+\tPINGROUP(28, pcie1_clk_req_n, qup_se1, _, _, qdss_cti_trig_out_a0, _, _, _, _),\n+\tPINGROUP(29, _, _, _, _, _, _, _, _, _),\n+\tPINGROUP(30, pcie1_wake, qup_se1, _, _, qdss_cti_trig_in_a0, _, _, _, _),\n+\tPINGROUP(31, pcie0_clk_req_n, mdc_slv0, _, qdss_cti_trig_out_a1, _, _, _, _, _),\n+\tPINGROUP(32, _, _, _, _, _, _, _, _, _),\n+\tPINGROUP(33, pcie0_wake, mdio_slv0, qdss_cti_trig_in_a1, _, _, _, _, _, _),\n+\tPINGROUP(34, audio_pri, atest_char_status0, qdss_cti_trig_in_b0, _, _, _, _, _, _),\n+\tPINGROUP(35, audio_pri, rx_los2, atest_char_status1, qdss_cti_trig_out_b1, _, _, _, _, _),\n+\tPINGROUP(36, audio_pri, _, rx_los1, atest_char_status2, _, _, _, _, _),\n+\tPINGROUP(37, audio_pri, rx_los0, atest_char_status3, _, qdss_cti_trig_in_b1, _, _, _, _),\n+\tPINGROUP(38, qup_se1, led2, gcc_plltest_bypassnl, qdss_tracedata_a, _, _, _, _, _),\n+\tPINGROUP(39, qup_se1, led1, led0, gcc_tlmm, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(40, qup_se4, rx_los2, audio_sec, gcc_plltest_resetn, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(41, qup_se4, rx_los1, audio_sec, qdss_tracedata_a, _, _, _, _, _),\n+\tPINGROUP(42, qup_se4, rx_los0, audio_sec, atest_tic_en, _, _, _, _, _),\n+\tPINGROUP(43, qup_se4, audio_sec, _, _, _, _, _, _, _),\n+\tPINGROUP(44, resout, _, _, _, _, _, _, _, _),\n+\tPINGROUP(45, pon_mux_sel, _, _, _, _, _, _, _, _),\n+\tPINGROUP(46, dg_out, atest_char_start, _, _, _, _, _, _, _),\n+\tPINGROUP(47, gpn_rx_los, mdc_slv2, qup_se5, _, _, _, _, _, _),\n+\tPINGROUP(48, pon_rx, qup_se5, _, _, _, _, _, _, _),\n+\tPINGROUP(49, gpn_tx_fault, mdio_slv2, qup_se5, audio_sec_mclk_out2, audio_sec_mclk_in2, _, _, _, _),\n+\tPINGROUP(50, gpn_tx_sd, qup_se5, audio_sec_mclk_out3, audio_sec_mclk_in3, _, _, _, _, _),\n+\tPINGROUP(51, gpn_tx_burst, qup_se5, _, _, _, _, _, _, _),\n+\tPINGROUP(52, qup_se2, qup_se5, qup_se4, qup_se5_l1, _, _, _, _, _),\n+\tPINGROUP(53, qup_se2, qup_se4, qup_se5_l1, _, _, _, _, _, _),\n+};\n+\n+static const char *ipq5210_get_function_name(struct udevice *dev, uint selector)\n+{\n+\treturn msm_pinctrl_functions[selector].name;\n+}\n+\n+static const char *ipq5210_get_pin_name(struct udevice *dev, uint selector)\n+{\n+\tsnprintf(pin_name, MAX_PIN_NAME_LEN, \"gpio%u\", selector);\n+\treturn pin_name;\n+}\n+\n+static int ipq5210_get_function_mux(unsigned int pin, uint selector)\n+{\n+\tunsigned int i;\n+\tconst msm_pin_function *func = ipq5210_pin_functions + pin;\n+\n+\tfor (i = 0; i < 10; i++)\n+\t\tif ((*func)[i] == selector)\n+\t\t\treturn i;\n+\n+\tpr_err(\"Can't find requested function for pin %u pin\\n\", pin);\n+\treturn -EINVAL;\n+}\n+\n+static const struct msm_pinctrl_data ipq5210_data = {\n+\t.pin_data = {\n+\t\t.pin_count = 53,\n+\t\t.special_pins_start = 53, /* There are no special pins */\n+\t},\n+\t.functions_count = ARRAY_SIZE(msm_pinctrl_functions),\n+\t.get_function_name = ipq5210_get_function_name,\n+\t.get_function_mux = ipq5210_get_function_mux,\n+\t.get_pin_name = ipq5210_get_pin_name,\n+};\n+\n+static const struct udevice_id msm_pinctrl_ids[] = {\n+\t{ .compatible = \"qcom,ipq5210-tlmm\", .data = (ulong)&ipq5210_data },\n+\t{ /* Sentinal */ }\n+};\n+\n+U_BOOT_DRIVER(pinctrl_ipq5210) = {\n+\t.name\t\t= \"pinctrl_ipq5210\",\n+\t.id\t\t= UCLASS_NOP,\n+\t.of_match\t= msm_pinctrl_ids,\n+\t.ops\t\t= &msm_pinctrl_ops,\n+\t.bind\t\t= msm_pinctrl_bind,\n+\t.flags = DM_FLAG_PRE_RELOC,\n+};\n", "prefixes": [ "v1", "4/9" ] }