Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2220793/?format=api
{ "id": 2220793, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220793/?format=api", "web_url": "http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260407-riscv_insn_table-v1-16-54b4736a1e77@gmail.com/", "project": { "id": 70, "url": "http://patchwork.ozlabs.org/api/1.1/projects/70/?format=api", "name": "Linux KVM RISC-V", "link_name": "kvm-riscv", "list_id": "kvm-riscv.lists.infradead.org", "list_email": "kvm-riscv@lists.infradead.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260407-riscv_insn_table-v1-16-54b4736a1e77@gmail.com>", "date": "2026-04-08T04:46:04", "name": "[16/16] riscv: Remove unused instruction headers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "92954914b969eb7a1f3967ee3ea6bf3e7b77f899", "submitter": { "id": 92521, "url": "http://patchwork.ozlabs.org/api/1.1/people/92521/?format=api", "name": "Charlie Jenkins via B4 Relay", "email": "devnull+thecharlesjenkins.gmail.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260407-riscv_insn_table-v1-16-54b4736a1e77@gmail.com/mbox/", "series": [ { "id": 499063, "url": "http://patchwork.ozlabs.org/api/1.1/series/499063/?format=api", "web_url": "http://patchwork.ozlabs.org/project/kvm-riscv/list/?series=499063", "date": "2026-04-08T04:45:48", "name": "riscv: Generate riscv instruction functions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499063/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220793/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220793/checks/", "tags": {}, "headers": { "Return-Path": "\n <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=BXqgp5yH;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=MqnsPJyy;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org;\n envelope-from=kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n [IPv6:2607:7c80:54:3::133])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fr9X11QQFz1yD6\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 08 Apr 2026 14:46:57 +1000 (AEST)", "from localhost ([::1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wAKoY-00000008EwP-0SvQ;\n\tWed, 08 Apr 2026 04:46:54 +0000", "from sea.source.kernel.org ([2600:3c0a:e001:78e:0:1991:8:25])\n\tby bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wAKoL-00000008EbZ-2aZH;\n\tWed, 08 Apr 2026 04:46:44 +0000", "from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58])\n\tby sea.source.kernel.org (Postfix) with ESMTP id 19D0A444BF;\n\tWed, 8 Apr 2026 04:46:38 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPS id ECF28C2BCB1;\n\tWed, 8 Apr 2026 04:46:37 +0000 (UTC)", "from aws-us-west-2-korg-lkml-1.web.codeaurora.org\n (localhost.localdomain [127.0.0.1])\n\tby smtp.lore.kernel.org (Postfix) with ESMTP id E6F09FD5F68;\n\tWed, 8 Apr 2026 04:46:37 +0000 (UTC)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help:\n\tList-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:\n\tMessage-Id:MIME-Version:Subject:Date:From:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=i9pkRAYdWATNDK1qIpa50D/VgBK7YZrZljHCUG4esFM=; b=BXqgp5yHprImoQ\n\tDW0FEVArZJYZ17VRXfcs+0FAUnuIV4shZFFcH2kU2HBLgNxowKM3etDHnN3p6/v2NV5ZMZXPPeZOC\n\topMRjuZrPsy88mwsUONXaoXr3GvYT0pLCy0D31SzU8LEn0R7DQHU1O5uz6lj70hfXsLANc/za7MlB\n\tZsKZdyILxli/+PkF5CjahwD0ugHcAKbbYefOL8b5WfMZ5wSmPDwDSTOE0vxD2u/oTPRiQQ9VPstxV\n\t3diji7wu0Y37i4KhFnZwHEeNE6Qg2P+gEkIhtZBvHPKDXs5ijydm5Yy5q+fxzG2fW16q+XVlxo1+5\n\t7Thr8BV22Ef4JfPChpzA==;", "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775623598;\n\tbh=8wPtZOdIunHOa0A3kGq4p12+3k4VUZ2hS7SUzFTnngc=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=MqnsPJyyziwfiG8mXsn4rMbLo8rTczSi882nYJpOl8DLm8kRRhwgOFo2CnBJ2yoF8\n\t JYliT5EjuwgmHvh8jPiQCa7ar+PbHsE88gn9+l3pG4WtuHyU5DqNk58/dBJB4CfF9v\n\t 8zAx2LMOcFxxPUI+WAw6+ckIQfo4YRI5IztsxqksQxtSlCubyguwTByoAsjX3bFauN\n\t Xfo8yUmb/dT1NsrH2lRZkaUQJi4OEBaLHPsJtk9FZsrzbPAmToRVF/D3mMKYPWwpX2\n\t vQDz4n1pp7LfZ3BChjUzKJZ2Epkzty2PC/J/kDdRPYiDDxXlLSy8UPA+tDJAb4LjpZ\n\t lVIENCSF9+uLA==" ], "From": "Charlie Jenkins via B4 Relay\n <devnull+thecharlesjenkins.gmail.com@kernel.org>", "Date": "Tue, 07 Apr 2026 21:46:04 -0700", "Subject": "[PATCH 16/16] riscv: Remove unused instruction headers", "MIME-Version": "1.0", "Message-Id": "<20260407-riscv_insn_table-v1-16-54b4736a1e77@gmail.com>", "References": "<20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com>", "In-Reply-To": "<20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com>", "To": "Paul Walmsley <pjw@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>,\n Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup@brainfault.org>,\n Atish Patra <atish.patra@linux.dev>, Conor Dooley <conor@kernel.org>,\n Paolo Bonzini <pbonzini@redhat.com>,\n Andrew Morton <akpm@linux-foundation.org>, Shuah Khan <shuah@kernel.org>", "Cc": "linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,\n kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,\n linux-kselftest@vger.kernel.org,\n Charlie Jenkins <thecharlesjenkins@gmail.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775623594; l=17862;\n i=thecharlesjenkins@gmail.com; s=2026030; h=from:subject:message-id;\n bh=rNrrN8s0yuy1PEPQ7SBnTqcnsQ6ilbK8WVkYbT03TFQ=;\n b=LccdWhFicRP3crEbMTj18OmRqxpEIBpHChEef+FneE6pJMfmahy01LguWeRl+ngOXMQCH+zOT\n Udk9nY3tuFUDmXprpLm6QBiDxtmy/wsgz7aF3GFlv617NgC26EDwUcl", "X-Developer-Key": "i=thecharlesjenkins@gmail.com; a=ed25519;\n pk=vpF2USrG+aB6CTbSt34rzJKsAVe/l+GAXo1IomCMETk=", "X-Endpoint-Received": "by B4 Relay for thecharlesjenkins@gmail.com/2026030\n with auth_id=663", "X-Original-From": "Charlie Jenkins <thecharlesjenkins@gmail.com>", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20260407_214641_753110_F37341C1 ", "X-CRM114-Status": "UNSURE ( 9.23 )", "X-CRM114-Notice": "Please train this message.", "X-Spam-Score": "0.0 (/)", "X-Spam-Report": "Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: From: Charlie Jenkins All usages of hard-coded riscv\n instruction\n have been migrated over to the generated instruction headers so the old\n macros\n can be deleted. Signed-off-by: Charlie Jenkins ---\n arch/riscv/include/asm/insn.h\n | 413 + 1 file changed, 4 insertions(+), 409 deletions(-)\n Content analysis details: (0.0 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n 0.0 UPPERCASE_50_75 message body is 50-75% uppercase\n 2.1 FREEMAIL_FORGED_REPLYTO Freemail in Reply-To, but not From", "X-BeenThere": "kvm-riscv@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<kvm-riscv.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/kvm-riscv>,\n <mailto:kvm-riscv-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/kvm-riscv/>", "List-Post": "<mailto:kvm-riscv@lists.infradead.org>", "List-Help": "<mailto:kvm-riscv-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/kvm-riscv>,\n <mailto:kvm-riscv-request@lists.infradead.org?subject=subscribe>", "Reply-To": "thecharlesjenkins@gmail.com", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"kvm-riscv\" <kvm-riscv-bounces@lists.infradead.org>", "Errors-To": "kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "From: Charlie Jenkins <thecharlesjenkins@gmail.com>\n\nAll usages of hard-coded riscv instruction have been migrated over to\nthe generated instruction headers so the old macros can be deleted.\n\nSigned-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com>\n---\n arch/riscv/include/asm/insn.h | 413 +-----------------------------------------\n 1 file changed, 4 insertions(+), 409 deletions(-)", "diff": "diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h\nindex 43440edc6f1d..6ea8dc08a290 100644\n--- a/arch/riscv/include/asm/insn.h\n+++ b/arch/riscv/include/asm/insn.h\n@@ -38,151 +38,22 @@ static __always_inline bool riscv_insn_is_##name(u32 _insn)\t\t\\\n \n #include <asm/insn_gen.h>\n \n-#define RV_INSN_FUNCT3_MASK\tGENMASK(14, 12)\n-#define RV_INSN_FUNCT3_OPOFF\t12\n #define RV_INSN_OPCODE_MASK\tGENMASK(6, 0)\n-#define RV_INSN_OPCODE_OPOFF\t0\n-#define RV_INSN_FUNCT12_OPOFF\t20\n-\n-#define RV_ENCODE_FUNCT3(f_)\t(RVG_FUNCT3_##f_ << RV_INSN_FUNCT3_OPOFF)\n-#define RV_ENCODE_FUNCT12(f_)\t(RVG_FUNCT12_##f_ << RV_INSN_FUNCT12_OPOFF)\n-\n-/* The bit field of immediate value in I-type instruction */\n-#define RV_I_IMM_SIGN_OPOFF\t31\n-#define RV_I_IMM_11_0_OPOFF\t20\n-#define RV_I_IMM_SIGN_OFF\t12\n-#define RV_I_IMM_11_0_OFF\t0\n-#define RV_I_IMM_11_0_MASK\tGENMASK(11, 0)\n-\n-/* The bit field of immediate value in J-type instruction */\n-#define RV_J_IMM_SIGN_OPOFF\t31\n-#define RV_J_IMM_10_1_OPOFF\t21\n-#define RV_J_IMM_11_OPOFF\t20\n-#define RV_J_IMM_19_12_OPOFF\t12\n-#define RV_J_IMM_SIGN_OFF\t20\n-#define RV_J_IMM_10_1_OFF\t1\n-#define RV_J_IMM_11_OFF\t\t11\n-#define RV_J_IMM_19_12_OFF\t12\n-#define RV_J_IMM_10_1_MASK\tGENMASK(9, 0)\n-#define RV_J_IMM_11_MASK\tGENMASK(0, 0)\n-#define RV_J_IMM_19_12_MASK\tGENMASK(7, 0)\n-\n-/*\n- * U-type IMMs contain the upper 20bits [31:20] of an immediate with\n- * the rest filled in by zeros, so no shifting required. Similarly,\n- * bit31 contains the signed state, so no sign extension necessary.\n- */\n-#define RV_U_IMM_SIGN_OPOFF\t31\n-#define RV_U_IMM_31_12_OPOFF\t0\n-#define RV_U_IMM_31_12_MASK\tGENMASK(31, 12)\n-\n-/* The bit field of immediate value in B-type instruction */\n-#define RV_B_IMM_SIGN_OPOFF\t31\n-#define RV_B_IMM_10_5_OPOFF\t25\n-#define RV_B_IMM_4_1_OPOFF\t8\n-#define RV_B_IMM_11_OPOFF\t7\n-#define RV_B_IMM_SIGN_OFF\t12\n-#define RV_B_IMM_10_5_OFF\t5\n-#define RV_B_IMM_4_1_OFF\t1\n-#define RV_B_IMM_11_OFF\t\t11\n-#define RV_B_IMM_10_5_MASK\tGENMASK(5, 0)\n-#define RV_B_IMM_4_1_MASK\tGENMASK(3, 0)\n-#define RV_B_IMM_11_MASK\tGENMASK(0, 0)\n-\n-/* The register offset in RVG instruction */\n-#define RVG_RS1_OPOFF\t\t15\n-#define RVG_RS2_OPOFF\t\t20\n-#define RVG_RD_OPOFF\t\t7\n-#define RVG_RS1_MASK\t\tGENMASK(4, 0)\n-#define RVG_RS2_MASK\t\tGENMASK(4, 0)\n-#define RVG_RD_MASK\t\tGENMASK(4, 0)\n-\n-/* The bit field of immediate value in RVC J instruction */\n-#define RVC_J_IMM_SIGN_OPOFF\t12\n-#define RVC_J_IMM_4_OPOFF\t11\n-#define RVC_J_IMM_9_8_OPOFF\t9\n-#define RVC_J_IMM_10_OPOFF\t8\n-#define RVC_J_IMM_6_OPOFF\t7\n-#define RVC_J_IMM_7_OPOFF\t6\n-#define RVC_J_IMM_3_1_OPOFF\t3\n-#define RVC_J_IMM_5_OPOFF\t2\n-#define RVC_J_IMM_SIGN_OFF\t11\n-#define RVC_J_IMM_4_OFF\t\t4\n-#define RVC_J_IMM_9_8_OFF\t8\n-#define RVC_J_IMM_10_OFF\t10\n-#define RVC_J_IMM_6_OFF\t\t6\n-#define RVC_J_IMM_7_OFF\t\t7\n-#define RVC_J_IMM_3_1_OFF\t1\n-#define RVC_J_IMM_5_OFF\t\t5\n-#define RVC_J_IMM_4_MASK\tGENMASK(0, 0)\n-#define RVC_J_IMM_9_8_MASK\tGENMASK(1, 0)\n-#define RVC_J_IMM_10_MASK\tGENMASK(0, 0)\n-#define RVC_J_IMM_6_MASK\tGENMASK(0, 0)\n-#define RVC_J_IMM_7_MASK\tGENMASK(0, 0)\n-#define RVC_J_IMM_3_1_MASK\tGENMASK(2, 0)\n-#define RVC_J_IMM_5_MASK\tGENMASK(0, 0)\n-\n-/* The bit field of immediate value in RVC B instruction */\n-#define RVC_B_IMM_SIGN_OPOFF\t12\n-#define RVC_B_IMM_4_3_OPOFF\t10\n-#define RVC_B_IMM_7_6_OPOFF\t5\n-#define RVC_B_IMM_2_1_OPOFF\t3\n-#define RVC_B_IMM_5_OPOFF\t2\n-#define RVC_B_IMM_SIGN_OFF\t8\n-#define RVC_B_IMM_4_3_OFF\t3\n-#define RVC_B_IMM_7_6_OFF\t6\n-#define RVC_B_IMM_2_1_OFF\t1\n-#define RVC_B_IMM_5_OFF\t\t5\n-#define RVC_B_IMM_4_3_MASK\tGENMASK(1, 0)\n-#define RVC_B_IMM_7_6_MASK\tGENMASK(1, 0)\n-#define RVC_B_IMM_2_1_MASK\tGENMASK(1, 0)\n-#define RVC_B_IMM_5_MASK\tGENMASK(0, 0)\n-\n-#define RVC_INSN_FUNCT4_MASK\tGENMASK(15, 12)\n-#define RVC_INSN_FUNCT4_OPOFF\t12\n-#define RVC_INSN_FUNCT3_MASK\tGENMASK(15, 13)\n-#define RVC_INSN_FUNCT3_OPOFF\t13\n-#define RVC_INSN_J_RS1_MASK\tGENMASK(11, 7)\n-#define RVC_INSN_J_RS2_MASK\tGENMASK(6, 2)\n-#define RVC_INSN_OPCODE_MASK\tGENMASK(1, 0)\n-#define RVC_ENCODE_FUNCT3(f_)\t(RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF)\n-#define RVC_ENCODE_FUNCT4(f_)\t(RVC_FUNCT4_##f_ << RVC_INSN_FUNCT4_OPOFF)\n-\n-/* The register offset in RVC op=C0 instruction */\n-#define RVC_C0_RS1_OPOFF\t7\n-#define RVC_C0_RS2_OPOFF\t2\n-#define RVC_C0_RD_OPOFF\t\t2\n-\n-/* The register offset in RVC op=C1 instruction */\n-#define RVC_C1_RS1_OPOFF\t7\n-#define RVC_C1_RS2_OPOFF\t2\n-#define RVC_C1_RD_OPOFF\t\t7\n-\n-/* The register offset in RVC op=C2 instruction */\n-#define RVC_C2_RS1_OPOFF\t7\n-#define RVC_C2_RS2_OPOFF\t2\n-#define RVC_C2_RD_OPOFF\t\t7\n-#define RVC_C2_RS1_MASK\t\tGENMASK(4, 0)\n \n /* parts of opcode for RVG*/\n-#define RVG_OPCODE_FENCE\t0x0f\n-#define RVG_OPCODE_AUIPC\t0x17\n #define RVG_OPCODE_BRANCH\t0x63\n-#define RVG_OPCODE_JALR\t\t0x67\n-#define RVG_OPCODE_JAL\t\t0x6f\n #define RVG_OPCODE_SYSTEM\t0x73\n #define RVG_SYSTEM_CSR_OFF\t20\n #define RVG_SYSTEM_CSR_MASK\tGENMASK(12, 0)\n \n+// THESE ARE ALL ACTUALLY USED\n /* parts of opcode for RVF, RVD and RVQ */\n #define RVFDQ_FL_FS_WIDTH_OFF\t12\n #define RVFDQ_FL_FS_WIDTH_MASK\tGENMASK(2, 0)\n-#define RVFDQ_FL_FS_WIDTH_W\t2\n-#define RVFDQ_FL_FS_WIDTH_D\t3\n-#define RVFDQ_LS_FS_WIDTH_Q\t4\n #define RVFDQ_OPCODE_FL\t\t0x07\n #define RVFDQ_OPCODE_FS\t\t0x27\n \n+// THESE ARE ALL ACTUALLY USED\n /* parts of opcode for RVV */\n #define RVV_OPCODE_VECTOR\t0x57\n #define RVV_VL_VS_WIDTH_8\t0\n@@ -192,72 +63,6 @@ static __always_inline bool riscv_insn_is_##name(u32 _insn)\t\t\\\n #define RVV_OPCODE_VL\t\tRVFDQ_OPCODE_FL\n #define RVV_OPCODE_VS\t\tRVFDQ_OPCODE_FS\n \n-/* parts of opcode for RVC*/\n-#define RVC_OPCODE_C0\t\t0x0\n-#define RVC_OPCODE_C1\t\t0x1\n-#define RVC_OPCODE_C2\t\t0x2\n-\n-/* parts of funct3 code for I, M, A extension*/\n-#define RVG_FUNCT3_JALR\t\t0x0\n-#define RVG_FUNCT3_BEQ\t\t0x0\n-#define RVG_FUNCT3_BNE\t\t0x1\n-#define RVG_FUNCT3_BLT\t\t0x4\n-#define RVG_FUNCT3_BGE\t\t0x5\n-#define RVG_FUNCT3_BLTU\t\t0x6\n-#define RVG_FUNCT3_BGEU\t\t0x7\n-\n-/* parts of funct3 code for C extension*/\n-#define RVC_FUNCT3_C_BEQZ\t0x6\n-#define RVC_FUNCT3_C_BNEZ\t0x7\n-#define RVC_FUNCT3_C_J\t\t0x5\n-#define RVC_FUNCT3_C_JAL\t0x1\n-#define RVC_FUNCT4_C_JR\t\t0x8\n-#define RVC_FUNCT4_C_JALR\t0x9\n-#define RVC_FUNCT4_C_EBREAK\t0x9\n-\n-#define RVG_FUNCT12_EBREAK\t0x1\n-#define RVG_FUNCT12_SRET\t0x102\n-\n-#define RVG_MATCH_AUIPC\t\t(RVG_OPCODE_AUIPC)\n-#define RVG_MATCH_JALR\t\t(RV_ENCODE_FUNCT3(JALR) | RVG_OPCODE_JALR)\n-#define RVG_MATCH_JAL\t\t(RVG_OPCODE_JAL)\n-#define RVG_MATCH_FENCE\t\t(RVG_OPCODE_FENCE)\n-#define RVG_MATCH_BEQ\t\t(RV_ENCODE_FUNCT3(BEQ) | RVG_OPCODE_BRANCH)\n-#define RVG_MATCH_BNE\t\t(RV_ENCODE_FUNCT3(BNE) | RVG_OPCODE_BRANCH)\n-#define RVG_MATCH_BLT\t\t(RV_ENCODE_FUNCT3(BLT) | RVG_OPCODE_BRANCH)\n-#define RVG_MATCH_BGE\t\t(RV_ENCODE_FUNCT3(BGE) | RVG_OPCODE_BRANCH)\n-#define RVG_MATCH_BLTU\t\t(RV_ENCODE_FUNCT3(BLTU) | RVG_OPCODE_BRANCH)\n-#define RVG_MATCH_BGEU\t\t(RV_ENCODE_FUNCT3(BGEU) | RVG_OPCODE_BRANCH)\n-#define RVG_MATCH_EBREAK\t(RV_ENCODE_FUNCT12(EBREAK) | RVG_OPCODE_SYSTEM)\n-#define RVG_MATCH_SRET\t\t(RV_ENCODE_FUNCT12(SRET) | RVG_OPCODE_SYSTEM)\n-#define RVC_MATCH_C_BEQZ\t(RVC_ENCODE_FUNCT3(C_BEQZ) | RVC_OPCODE_C1)\n-#define RVC_MATCH_C_BNEZ\t(RVC_ENCODE_FUNCT3(C_BNEZ) | RVC_OPCODE_C1)\n-#define RVC_MATCH_C_J\t\t(RVC_ENCODE_FUNCT3(C_J) | RVC_OPCODE_C1)\n-#define RVC_MATCH_C_JAL\t\t(RVC_ENCODE_FUNCT3(C_JAL) | RVC_OPCODE_C1)\n-#define RVC_MATCH_C_JR\t\t(RVC_ENCODE_FUNCT4(C_JR) | RVC_OPCODE_C2)\n-#define RVC_MATCH_C_JALR\t(RVC_ENCODE_FUNCT4(C_JALR) | RVC_OPCODE_C2)\n-#define RVC_MATCH_C_EBREAK\t(RVC_ENCODE_FUNCT4(C_EBREAK) | RVC_OPCODE_C2)\n-\n-#define RVG_MASK_AUIPC\t\t(RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_JALR\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_JAL\t\t(RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_FENCE\t\t(RV_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_JALR\t\t(RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_JR\t\t(RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_JAL\t\t(RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_J\t\t(RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)\n-#define RVG_MASK_BEQ\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_BNE\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_BLT\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_BGE\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_BLTU\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVG_MASK_BGEU\t\t(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_BEQZ\t\t(RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_BNEZ\t\t(RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)\n-#define RVC_MASK_C_EBREAK\t0xffff\n-#define RVG_MASK_EBREAK\t\t0xffffffff\n-#define RVG_MASK_SRET\t\t0xffffffff\n-\n #define __INSN_LENGTH_MASK\t_UL(0x3)\n #define __INSN_LENGTH_GE_32\t_UL(0x3)\n #define __INSN_OPCODE_MASK\t_UL(0x7F)\n@@ -275,236 +80,26 @@ static __always_inline bool riscv_insn_is_branch(u32 code)\n \treturn (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH;\n }\n \n-#define INSN_MATCH_LB\t\t0x3\n-#define INSN_MASK_LB\t\t0x707f\n-#define INSN_MATCH_LH\t\t0x1003\n-#define INSN_MASK_LH\t\t0x707f\n-#define INSN_MATCH_LW\t\t0x2003\n-#define INSN_MASK_LW\t\t0x707f\n-#define INSN_MATCH_LD\t\t0x3003\n-#define INSN_MASK_LD\t\t0x707f\n-#define INSN_MATCH_LBU\t\t0x4003\n-#define INSN_MASK_LBU\t\t0x707f\n-#define INSN_MATCH_LHU\t\t0x5003\n-#define INSN_MASK_LHU\t\t0x707f\n-#define INSN_MATCH_LWU\t\t0x6003\n-#define INSN_MASK_LWU\t\t0x707f\n-#define INSN_MATCH_SB\t\t0x23\n-#define INSN_MASK_SB\t\t0x707f\n-#define INSN_MATCH_SH\t\t0x1023\n-#define INSN_MASK_SH\t\t0x707f\n-#define INSN_MATCH_SW\t\t0x2023\n-#define INSN_MASK_SW\t\t0x707f\n-#define INSN_MATCH_SD\t\t0x3023\n-#define INSN_MASK_SD\t\t0x707f\n-\n-#define INSN_MATCH_C_LD\t\t0x6000\n-#define INSN_MASK_C_LD\t\t0xe003\n-#define INSN_MATCH_C_SD\t\t0xe000\n-#define INSN_MASK_C_SD\t\t0xe003\n-#define INSN_MATCH_C_LW\t\t0x4000\n-#define INSN_MASK_C_LW\t\t0xe003\n-#define INSN_MATCH_C_SW\t\t0xc000\n-#define INSN_MASK_C_SW\t\t0xe003\n-#define INSN_MATCH_C_LDSP\t0x6002\n-#define INSN_MASK_C_LDSP\t0xe003\n-#define INSN_MATCH_C_SDSP\t0xe002\n-#define INSN_MASK_C_SDSP\t0xe003\n-#define INSN_MATCH_C_LWSP\t0x4002\n-#define INSN_MASK_C_LWSP\t0xe003\n-#define INSN_MATCH_C_SWSP\t0xc002\n-#define INSN_MASK_C_SWSP\t0xe003\n-\n #define INSN_OPCODE_MASK\t0x007c\n #define INSN_OPCODE_SHIFT\t2\n #define INSN_OPCODE_SYSTEM\t28\n \n-#define INSN_MASK_WFI\t\t0xffffffff\n-#define INSN_MATCH_WFI\t\t0x10500073\n-\n-#define INSN_MASK_WRS\t\t0xffffffff\n-#define INSN_MATCH_WRS\t\t0x00d00073\n-\n-#define INSN_MATCH_CSRRW\t0x1073\n-#define INSN_MASK_CSRRW\t\t0x707f\n-#define INSN_MATCH_CSRRS\t0x2073\n-#define INSN_MASK_CSRRS\t\t0x707f\n-#define INSN_MATCH_CSRRC\t0x3073\n-#define INSN_MASK_CSRRC\t\t0x707f\n-#define INSN_MATCH_CSRRWI\t0x5073\n-#define INSN_MASK_CSRRWI\t0x707f\n-#define INSN_MATCH_CSRRSI\t0x6073\n-#define INSN_MASK_CSRRSI\t0x707f\n-#define INSN_MATCH_CSRRCI\t0x7073\n-#define INSN_MASK_CSRRCI\t0x707f\n-\n-#define INSN_MATCH_FLW\t\t0x2007\n-#define INSN_MASK_FLW\t\t0x707f\n-#define INSN_MATCH_FLD\t\t0x3007\n-#define INSN_MASK_FLD\t\t0x707f\n-#define INSN_MATCH_FLQ\t\t0x4007\n-#define INSN_MASK_FLQ\t\t0x707f\n-#define INSN_MATCH_FSW\t\t0x2027\n-#define INSN_MASK_FSW\t\t0x707f\n-#define INSN_MATCH_FSD\t\t0x3027\n-#define INSN_MASK_FSD\t\t0x707f\n-#define INSN_MATCH_FSQ\t\t0x4027\n-#define INSN_MASK_FSQ\t\t0x707f\n-\n-#define INSN_MATCH_C_FLD\t0x2000\n-#define INSN_MASK_C_FLD\t\t0xe003\n-#define INSN_MATCH_C_FLW\t0x6000\n-#define INSN_MASK_C_FLW\t\t0xe003\n-#define INSN_MATCH_C_FSD\t0xa000\n-#define INSN_MASK_C_FSD\t\t0xe003\n-#define INSN_MATCH_C_FSW\t0xe000\n-#define INSN_MASK_C_FSW\t\t0xe003\n-#define INSN_MATCH_C_FLDSP\t0x2002\n-#define INSN_MASK_C_FLDSP\t0xe003\n-#define INSN_MATCH_C_FSDSP\t0xa002\n-#define INSN_MASK_C_FSDSP\t0xe003\n-#define INSN_MATCH_C_FLWSP\t0x6002\n-#define INSN_MASK_C_FLWSP\t0xe003\n-#define INSN_MATCH_C_FSWSP\t0xe002\n-#define INSN_MASK_C_FSWSP\t0xe003\n-\n-#define INSN_MATCH_C_LHU\t\t0x8400\n-#define INSN_MASK_C_LHU\t\t\t0xfc43\n-#define INSN_MATCH_C_LH\t\t\t0x8440\n-#define INSN_MASK_C_LH\t\t\t0xfc43\n-#define INSN_MATCH_C_SH\t\t\t0x8c00\n-#define INSN_MASK_C_SH\t\t\t0xfc43\n-\n #define INSN_16BIT_MASK\t\t0x3\n #define INSN_IS_16BIT(insn)\t(((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)\n #define INSN_LEN(insn)\t\t(INSN_IS_16BIT(insn) ? 2 : 4)\n \n-#define SHIFT_RIGHT(x, y)\t\t\\\n-\t((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))\n-\n #define REG_MASK\t\t\t\\\n \t((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))\n \n-#define REG_OFFSET(insn, pos)\t\t\\\n-\t(SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)\n-\n-#define REG_PTR(insn, pos, regs)\t\\\n-\t((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))\n-\n-#define GET_RS1(insn, regs)\t(*REG_PTR(insn, SH_RS1, regs))\n-#define GET_RS2(insn, regs)\t(*REG_PTR(insn, SH_RS2, regs))\n-#define GET_RS1S(insn, regs)\t(*REG_PTR(RVC_RS1S(insn), 0, regs))\n-#define GET_RS2S(insn, regs)\t(*REG_PTR(RVC_RS2S(insn), 0, regs))\n-#define GET_RS2C(insn, regs)\t(*REG_PTR(insn, SH_RS2C, regs))\n-#define GET_SP(regs)\t\t(*REG_PTR(2, 0, regs))\n-#define SET_RD(insn, regs, val)\t(*REG_PTR(insn, SH_RD, regs) = (val))\n-#define IMM_I(insn)\t\t((s32)(insn) >> 20)\n-#define IMM_S(insn)\t\t(((s32)(insn) >> 25 << 5) | \\\n-\t\t\t\t (s32)(((insn) >> 7) & 0x1f))\n-\n-#define SH_RD\t\t\t7\n-#define SH_RS1\t\t\t15\n-#define SH_RS2\t\t\t20\n-#define SH_RS2C\t\t\t2\n-#define MASK_RX\t\t\t0x1f\n-\n #if defined(CONFIG_64BIT)\n #define LOG_REGBYTES\t\t3\n #else\n #define LOG_REGBYTES\t\t2\n #endif\n \n-#define MASK_FUNCT3\t\t0x7000\n-\n-#define GET_FUNCT3(insn)\t(((insn) >> 12) & 7)\n-\n-#define RV_IMM_SIGN(x)\t\t(-(((x) >> 31) & 1))\n-#define RVC_IMM_SIGN(x)\t\t(-(((x) >> 12) & 1))\n-#define RV_X_MASK(X, s, mask)\t(((X) >> (s)) & (mask))\n-#define RV_X(X, s, n)\t\tRV_X_MASK(X, s, ((1 << (n)) - 1))\n-#define RVC_LW_IMM(x)\t\t((RV_X(x, 6, 1) << 2) | \\\n-\t\t\t\t (RV_X(x, 10, 3) << 3) | \\\n-\t\t\t\t (RV_X(x, 5, 1) << 6))\n-#define RVC_LD_IMM(x)\t\t((RV_X(x, 10, 3) << 3) | \\\n-\t\t\t\t (RV_X(x, 5, 2) << 6))\n-#define RVC_LWSP_IMM(x)\t\t((RV_X(x, 4, 3) << 2) | \\\n-\t\t\t\t (RV_X(x, 12, 1) << 5) | \\\n-\t\t\t\t (RV_X(x, 2, 2) << 6))\n-#define RVC_LDSP_IMM(x)\t\t((RV_X(x, 5, 2) << 3) | \\\n-\t\t\t\t (RV_X(x, 12, 1) << 5) | \\\n-\t\t\t\t (RV_X(x, 2, 3) << 6))\n-#define RVC_SWSP_IMM(x)\t\t((RV_X(x, 9, 4) << 2) | \\\n-\t\t\t\t (RV_X(x, 7, 2) << 6))\n-#define RVC_SDSP_IMM(x)\t\t((RV_X(x, 10, 3) << 3) | \\\n-\t\t\t\t (RV_X(x, 7, 3) << 6))\n-#define RVC_RS1S(insn)\t\t(8 + RV_X(insn, SH_RD, 3))\n-#define RVC_RS2S(insn)\t\t(8 + RV_X(insn, SH_RS2C, 3))\n-#define RVC_RS2(insn)\t\tRV_X(insn, SH_RS2C, 5)\n-#define RVC_X(X, s, mask)\tRV_X_MASK(X, s, mask)\n-\n-#define RV_EXTRACT_FUNCT3(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RV_INSN_FUNCT3_OPOFF, \\\n-\t\t RV_INSN_FUNCT3_MASK >> RV_INSN_FUNCT3_OPOFF)); })\n-\n-#define RV_EXTRACT_RS1_REG(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })\n-\n-#define RV_EXTRACT_RS2_REG(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RVG_RS2_OPOFF, RVG_RS2_MASK)); })\n-\n-#define RV_EXTRACT_RD_REG(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })\n-\n-#define RV_EXTRACT_UTYPE_IMM(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })\n-\n-#define RV_EXTRACT_JTYPE_IMM(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \\\n-\t(RV_X_MASK(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \\\n-\t(RV_X_MASK(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \\\n-\t(RV_IMM_SIGN(x_) << RV_J_IMM_SIGN_OFF); })\n-\n-#define RV_EXTRACT_ITYPE_IMM(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \\\n-\t(RV_IMM_SIGN(x_) << RV_I_IMM_SIGN_OFF); })\n-\n-#define RV_EXTRACT_BTYPE_IMM(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \\\n-\t(RV_X_MASK(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \\\n-\t(RV_X_MASK(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \\\n-\t(RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); })\n-\n-#define RVC_EXTRACT_C2_RS1_REG(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RV_X_MASK(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })\n-\n-#define RVC_EXTRACT_JTYPE_IMM(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) << RVC_J_IMM_3_1_OFF) | \\\n-\t(RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) << RVC_J_IMM_4_OFF) | \\\n-\t(RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) << RVC_J_IMM_5_OFF) | \\\n-\t(RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) << RVC_J_IMM_6_OFF) | \\\n-\t(RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) << RVC_J_IMM_7_OFF) | \\\n-\t(RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) << RVC_J_IMM_9_8_OFF) | \\\n-\t(RVC_X(x_, RVC_J_IMM_10_OPOFF, RVC_J_IMM_10_MASK) << RVC_J_IMM_10_OFF) | \\\n-\t(RVC_IMM_SIGN(x_) << RVC_J_IMM_SIGN_OFF); })\n-\n-#define RVC_EXTRACT_BTYPE_IMM(x) \\\n-\t({typeof(x) x_ = (x); \\\n-\t(RVC_X(x_, RVC_B_IMM_2_1_OPOFF, RVC_B_IMM_2_1_MASK) << RVC_B_IMM_2_1_OFF) | \\\n-\t(RVC_X(x_, RVC_B_IMM_4_3_OPOFF, RVC_B_IMM_4_3_MASK) << RVC_B_IMM_4_3_OFF) | \\\n-\t(RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \\\n-\t(RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \\\n-\t(RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })\n+#define RV_X_MASK(X, s, mask) (((X) >> (s)) & (mask))\n \n+// These three are used by vector stuff\n #define RVG_EXTRACT_SYSTEM_CSR(x) \\\n \t({typeof(x) x_ = (x); RV_X_MASK(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })\n \n", "prefixes": [ "16/16" ] }