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GET /api/1.1/patches/2220788/?format=api
{ "id": 2220788, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220788/?format=api", "web_url": "http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260407-riscv_insn_table-v1-6-54b4736a1e77@gmail.com/", "project": { "id": 70, "url": "http://patchwork.ozlabs.org/api/1.1/projects/70/?format=api", "name": "Linux KVM RISC-V", "link_name": "kvm-riscv", "list_id": "kvm-riscv.lists.infradead.org", "list_email": "kvm-riscv@lists.infradead.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260407-riscv_insn_table-v1-6-54b4736a1e77@gmail.com>", "date": "2026-04-08T04:45:54", "name": "[06/16] riscv: Use generated instruction headers for misaligned loads/stores", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1ef1befd4eb6d4ad9648d83d6bedea0e667dea40", "submitter": { "id": 92521, "url": "http://patchwork.ozlabs.org/api/1.1/people/92521/?format=api", "name": "Charlie Jenkins via B4 Relay", "email": "devnull+thecharlesjenkins.gmail.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260407-riscv_insn_table-v1-6-54b4736a1e77@gmail.com/mbox/", "series": [ { "id": 499063, "url": "http://patchwork.ozlabs.org/api/1.1/series/499063/?format=api", "web_url": "http://patchwork.ozlabs.org/project/kvm-riscv/list/?series=499063", "date": "2026-04-08T04:45:48", "name": "riscv: Generate riscv instruction functions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499063/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220788/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220788/checks/", "tags": {}, "headers": { "Return-Path": "\n <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=dmt64f6J;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=MV7mcVii;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help:\n\tList-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:\n\tMessage-Id:MIME-Version:Subject:Date:From:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=Xd33hpoVd8/aUAIqW7irKe46/8bSgUPpuFyoPAdIqwc=; b=dmt64f6JbynBwk\n\tNBTqvBSSgHLl0vmJh8hcRF1JqB6yQQ/LH89r89hXDUDVkVluKoWmVLvq7NSse0uOELllKjXhVKeQH\n\tHVF1brMvvcv+YtaZtB5HU07joSvg5SemeFsL9x1OlZGjki5vFRJfbVSE/r21FZ/6ls7Jv14Vlr6G3\n\te9IW1v5eU+yDaykDfp7WVr1jn6x1yJcA4wcHnrjdCCEtOCwW4rcmpYrC2dTKqHCucqheizD6K3Yjv\n\tXWcojP4MkXRn8gSjUFKNvGFkRGYmgXDF3L5lYO0/xhx46f8FLv/ihZsS6dM3KEfZ48AV8TBu4zeA7\n\t5wqXDouY97FpbnMa09oA==;", "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775623596;\n\tbh=HNvGZP/PuCqYLkCx9Gaq3wYlwoREaAJofqqabmC45W4=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=MV7mcViiU6SJZhgS1ephI7soVRhBzrBF7ZxL4+Zb5NUKxqb7AtZGmk1SotbRGnaVy\n\t Twj0wNf7s6wtWNcX86n65bVQ+2qGf0rErQpZ0lbWEzkErx8lunYq3IN2QWoCQ2mSf8\n\t nk+1cYIQR2bWZGjdDFCetzLnE9zg5tP6f3k9WK0oIZkAzLTzJW9RtprWuTqAc5yM+K\n\t jYkGD1mAB6zGYlrRVlmfTCi87XidL1W4ibydBNP6SQgz4Sh+oL+ah/2ZDRLDBUWbLz\n\t vOWzLrn/rGDej1ch7HAdkJL7iCDgU+clO6arzn+BzDAmfTxHvip9Wu/67FsrKVhRoO\n\t Wr1dN65KI617g==" ], "From": "Charlie Jenkins via B4 Relay\n <devnull+thecharlesjenkins.gmail.com@kernel.org>", "Date": "Tue, 07 Apr 2026 21:45:54 -0700", "Subject": "[PATCH 06/16] riscv: Use generated instruction headers for\n misaligned loads/stores", "MIME-Version": "1.0", "Message-Id": "<20260407-riscv_insn_table-v1-6-54b4736a1e77@gmail.com>", "References": "<20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com>", "In-Reply-To": "<20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com>", "To": "Paul Walmsley <pjw@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>,\n Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup@brainfault.org>,\n Atish Patra <atish.patra@linux.dev>, Conor Dooley <conor@kernel.org>,\n Paolo Bonzini <pbonzini@redhat.com>,\n Andrew Morton <akpm@linux-foundation.org>, Shuah Khan <shuah@kernel.org>", "Cc": "linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,\n kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,\n linux-kselftest@vger.kernel.org,\n Charlie Jenkins <thecharlesjenkins@gmail.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: From: Charlie Jenkins Migrate the misaligned loads/store\n code\n to use the generated instruction headers instead of the hand-written\n instruction\n composition functions. Signed-off-by: Charlie Jenkins\n Content analysis details: (-0.0 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n 0.0 RCVD_IN_VALIDITY_CERTIFIED_BLOCKED RBL: ADMINISTRATOR NOTICE: The\n query to Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [172.234.252.31 listed in\n sa-trusted.bondedsender.org]\n 0.0 RCVD_IN_VALIDITY_SAFE_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to\n Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [172.234.252.31 listed in sa-accredit.habeas.com]\n 0.0 RCVD_IN_VALIDITY_RPBL_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to\n Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [172.234.252.31 listed in\n bl.score.senderscore.com]\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n 2.1 FREEMAIL_FORGED_REPLYTO Freemail in Reply-To, but not From", "X-BeenThere": "kvm-riscv@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<kvm-riscv.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/kvm-riscv>,\n <mailto:kvm-riscv-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/kvm-riscv/>", "List-Post": "<mailto:kvm-riscv@lists.infradead.org>", "List-Help": "<mailto:kvm-riscv-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/kvm-riscv>,\n <mailto:kvm-riscv-request@lists.infradead.org?subject=subscribe>", "Reply-To": "thecharlesjenkins@gmail.com", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"kvm-riscv\" <kvm-riscv-bounces@lists.infradead.org>", "Errors-To": "kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "From: Charlie Jenkins <thecharlesjenkins@gmail.com>\n\nMigrate the misaligned loads/store code to use the generated instruction\nheaders instead of the hand-written instruction composition functions.\n\nSigned-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com>\n\n---\n\nSimilar to the other patches of this series, I extracted out the logic\nof this function and brute forced all possible inputs to validate that\nthe outputs are the same. To verify this change in the kernel, I booted\non Spike and used the misaligned access checker which does some\nmisaligned accesses.\n---\n arch/riscv/kernel/traps_misaligned.c | 183 ++++++++++++++++-------------------\n 1 file changed, 83 insertions(+), 100 deletions(-)", "diff": "diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c\nindex 2a27d3ff4ac6..a36ea0994ae8 100644\n--- a/arch/riscv/kernel/traps_misaligned.c\n+++ b/arch/riscv/kernel/traps_misaligned.c\n@@ -22,15 +22,11 @@\n \n #ifdef CONFIG_FPU\n \n-#define FP_GET_RD(insn)\t\t(insn >> 7 & 0x1F)\n-\n extern void put_f32_reg(unsigned long fp_reg, unsigned long value);\n \n-static int set_f32_rd(unsigned long insn, struct pt_regs *regs,\n+static int set_f32_rd(unsigned long fp_reg, struct pt_regs *regs,\n \t\t unsigned long val)\n {\n-\tunsigned long fp_reg = FP_GET_RD(insn);\n-\n \tput_f32_reg(fp_reg, val);\n \tregs->status |= SR_FS_DIRTY;\n \n@@ -39,9 +35,8 @@ static int set_f32_rd(unsigned long insn, struct pt_regs *regs,\n \n extern void put_f64_reg(unsigned long fp_reg, unsigned long value);\n \n-static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val)\n+static int set_f64_rd(unsigned long fp_reg, struct pt_regs *regs, u64 val)\n {\n-\tunsigned long fp_reg = FP_GET_RD(insn);\n \tunsigned long value;\n \n #if __riscv_xlen == 32\n@@ -58,10 +53,8 @@ static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val)\n #if __riscv_xlen == 32\n extern void get_f64_reg(unsigned long fp_reg, u64 *value);\n \n-static u64 get_f64_rs(unsigned long insn, u8 fp_reg_offset,\n-\t\t struct pt_regs *regs)\n+static u64 get_f64_rs(unsigned long fp_reg, struct pt_regs *regs)\n {\n-\tunsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F;\n \tu64 val;\n \n \tget_f64_reg(fp_reg, &val);\n@@ -73,10 +66,8 @@ static u64 get_f64_rs(unsigned long insn, u8 fp_reg_offset,\n \n extern unsigned long get_f64_reg(unsigned long fp_reg);\n \n-static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset,\n-\t\t\t\tstruct pt_regs *regs)\n+static unsigned long get_f64_rs(unsigned long fp_reg, struct pt_regs *regs)\n {\n-\tunsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F;\n \tunsigned long val;\n \n \tval = get_f64_reg(fp_reg);\n@@ -89,10 +80,8 @@ static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset,\n \n extern unsigned long get_f32_reg(unsigned long fp_reg);\n \n-static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset,\n-\t\t\t\tstruct pt_regs *regs)\n+static unsigned long get_f32_rs(unsigned long fp_reg, struct pt_regs *regs)\n {\n-\tunsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F;\n \tunsigned long val;\n \n \tval = get_f32_reg(fp_reg);\n@@ -107,28 +96,18 @@ static void set_f32_rd(unsigned long insn, struct pt_regs *regs,\n \n static void set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) {}\n \n-static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset,\n-\t\t\t\tstruct pt_regs *regs)\n+static unsigned long get_f64_rs(unsigned long fp_reg, struct pt_regs *regs)\n {\n \treturn 0;\n }\n \n-static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset,\n-\t\t\t\tstruct pt_regs *regs)\n+static unsigned long get_f32_rs(unsigned long fp_reg, struct pt_regs *regs)\n {\n \treturn 0;\n }\n \n #endif\n \n-#define GET_F64_RS2(insn, regs) (get_f64_rs(insn, 20, regs))\n-#define GET_F64_RS2C(insn, regs) (get_f64_rs(insn, 2, regs))\n-#define GET_F64_RS2S(insn, regs) (get_f64_rs(RVC_RS2S(insn), 0, regs))\n-\n-#define GET_F32_RS2(insn, regs) (get_f32_rs(insn, 20, regs))\n-#define GET_F32_RS2C(insn, regs) (get_f32_rs(insn, 2, regs))\n-#define GET_F32_RS2S(insn, regs) (get_f32_rs(RVC_RS2S(insn), 0, regs))\n-\n #define __read_insn(regs, insn, insn_addr, type)\t\\\n ({\t\t\t\t\t\t\t\\\n \tint __ret;\t\t\t\t\t\\\n@@ -217,13 +196,13 @@ static int handle_vector_misaligned_load(struct pt_regs *regs)\n }\n #endif\n \n-static int handle_scalar_misaligned_load(struct pt_regs *regs)\n+static noinline int handle_scalar_misaligned_load(struct pt_regs *regs)\n {\n \tunion reg_data val;\n \tunsigned long epc = regs->epc;\n \tunsigned long insn;\n \tunsigned long addr = regs->badaddr;\n-\tint fp = 0, shift = 0, len = 0;\n+\tint fp = 0, shift = 0, len = 0, rd = 0;\n \n \tperf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);\n \n@@ -240,68 +219,71 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)\n \n \tregs->epc = 0;\n \n-\tif ((insn & INSN_MASK_LW) == INSN_MATCH_LW) {\n+\tif (riscv_insn_is_lw(insn)) {\n \t\tlen = 4;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-#if defined(CONFIG_64BIT)\n-\t} else if ((insn & INSN_MASK_LD) == INSN_MATCH_LD) {\n+\t\trd = riscv_insn_lw_extract_xd(insn);\n+\t} else if (riscv_insn_is_ld(insn)) {\n \t\tlen = 8;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-\t} else if ((insn & INSN_MASK_LWU) == INSN_MATCH_LWU) {\n+\t\trd = riscv_insn_ld_extract_xd(insn);\n+\t} else if (riscv_insn_is_lwu(insn)) {\n \t\tlen = 4;\n-#endif\n-\t} else if ((insn & INSN_MASK_FLD) == INSN_MATCH_FLD) {\n+\t\trd = riscv_insn_lwu_extract_xd(insn);\n+\t} else if (riscv_insn_is_fld(insn)) {\n \t\tfp = 1;\n \t\tlen = 8;\n-\t} else if ((insn & INSN_MASK_FLW) == INSN_MATCH_FLW) {\n+\t\trd = riscv_insn_fld_extract_fd(insn);\n+\t} else if (riscv_insn_is_flw(insn)) {\n \t\tfp = 1;\n \t\tlen = 4;\n-\t} else if ((insn & INSN_MASK_LH) == INSN_MATCH_LH) {\n+\t\trd = riscv_insn_flw_extract_fd(insn);\n+\t} else if (riscv_insn_is_lh(insn)) {\n \t\tlen = 2;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-\t} else if ((insn & INSN_MASK_LHU) == INSN_MATCH_LHU) {\n+\t\trd = riscv_insn_lh_extract_xd(insn);\n+\t} else if (riscv_insn_is_lhu(insn)) {\n \t\tlen = 2;\n-#if defined(CONFIG_64BIT)\n-\t} else if ((insn & INSN_MASK_C_LD) == INSN_MATCH_C_LD) {\n+\t\trd = riscv_insn_lhu_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_ld(insn)) {\n \t\tlen = 8;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-\t\tinsn = RVC_RS2S(insn) << SH_RD;\n-\t} else if ((insn & INSN_MASK_C_LDSP) == INSN_MATCH_C_LDSP &&\n-\t\t ((insn >> SH_RD) & 0x1f)) {\n+\t\trd = (8 + riscv_insn_c_ld_extract_xd(insn));\n+\t} else if (riscv_insn_is_c_ldsp(insn)) {\n \t\tlen = 8;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-#endif\n-\t} else if ((insn & INSN_MASK_C_LW) == INSN_MATCH_C_LW) {\n+\t\trd = riscv_insn_c_ldsp_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_lw(insn)) {\n \t\tlen = 4;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-\t\tinsn = RVC_RS2S(insn) << SH_RD;\n-\t} else if ((insn & INSN_MASK_C_LWSP) == INSN_MATCH_C_LWSP &&\n-\t\t ((insn >> SH_RD) & 0x1f)) {\n+\t\trd = (8 + riscv_insn_c_lw_extract_xd(insn));\n+\t} else if (riscv_insn_is_c_lwsp(insn)) {\n \t\tlen = 4;\n \t\tshift = 8 * (sizeof(unsigned long) - len);\n-\t} else if ((insn & INSN_MASK_C_FLD) == INSN_MATCH_C_FLD) {\n+\t\trd = riscv_insn_c_lwsp_extract_xd(insn);\n+\t} else if (riscv_insn_is_c_fld(insn)) {\n \t\tfp = 1;\n \t\tlen = 8;\n-\t\tinsn = RVC_RS2S(insn) << SH_RD;\n-\t} else if ((insn & INSN_MASK_C_FLDSP) == INSN_MATCH_C_FLDSP) {\n+\t\trd = (8 + riscv_insn_c_fld_extract_fd(insn));\n+\t} else if (riscv_insn_is_c_fldsp(insn)) {\n \t\tfp = 1;\n \t\tlen = 8;\n-#if defined(CONFIG_32BIT)\n-\t} else if ((insn & INSN_MASK_C_FLW) == INSN_MATCH_C_FLW) {\n+\t\trd = riscv_insn_c_fldsp_extract_fd(insn);\n+\t} else if (riscv_insn_is_c_flw(insn)) {\n \t\tfp = 1;\n \t\tlen = 4;\n-\t\tinsn = RVC_RS2S(insn) << SH_RD;\n-\t} else if ((insn & INSN_MASK_C_FLWSP) == INSN_MATCH_C_FLWSP) {\n+\t\trd = (8 + riscv_insn_c_flw_extract_fd(insn));\n+\t} else if (riscv_insn_is_c_flwsp(insn)) {\n \t\tfp = 1;\n \t\tlen = 4;\n-#endif\n-\t} else if ((insn & INSN_MASK_C_LHU) == INSN_MATCH_C_LHU) {\n+\t\trd = riscv_insn_c_flwsp_extract_fd(insn);\n+\t} else if (riscv_insn_is_c_lhu(insn)) {\n \t\tlen = 2;\n-\t\tinsn = RVC_RS2S(insn) << SH_RD;\n-\t} else if ((insn & INSN_MASK_C_LH) == INSN_MATCH_C_LH) {\n+\t\trd = (8 + riscv_insn_c_lhu_extract_xd(insn));\n+\t} else if (riscv_insn_is_c_lh(insn)) {\n \t\tlen = 2;\n-\t\tshift = 8 * (sizeof(ulong) - len);\n-\t\tinsn = RVC_RS2S(insn) << SH_RD;\n+\t\tshift = 8 * (sizeof(unsigned long) - len);\n+\t\trd = (8 + riscv_insn_c_lh_extract_xd(insn));\n \t} else {\n \t\tregs->epc = epc;\n \t\treturn -1;\n@@ -319,11 +301,11 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs)\n \t}\n \n \tif (!fp)\n-\t\tSET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);\n+\t\t*(unsigned long *)((unsigned long *)regs + rd) = val.data_ulong << shift;\n \telse if (len == 8)\n-\t\tset_f64_rd(insn, regs, val.data_u64);\n+\t\tset_f64_rd(rd, regs, val.data_u64);\n \telse\n-\t\tset_f32_rd(insn, regs, val.data_ulong);\n+\t\tset_f32_rd(rd, regs, val.data_ulong);\n \n \tregs->epc = epc + INSN_LEN(insn);\n \n@@ -336,7 +318,7 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs)\n \tunsigned long epc = regs->epc;\n \tunsigned long insn;\n \tunsigned long addr = regs->badaddr;\n-\tint len = 0, fp = 0;\n+\tint fp = 0, len = 0, rd = 0;\n \n \tperf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);\n \n@@ -351,67 +333,68 @@ static int handle_scalar_misaligned_store(struct pt_regs *regs)\n \n \tregs->epc = 0;\n \n-\tval.data_ulong = GET_RS2(insn, regs);\n-\n-\tif ((insn & INSN_MASK_SW) == INSN_MATCH_SW) {\n+\tif (riscv_insn_is_sw(insn)) {\n \t\tlen = 4;\n-#if defined(CONFIG_64BIT)\n-\t} else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) {\n+\t\trd = riscv_insn_sw_extract_xs2(insn);\n+\t} else if (riscv_insn_is_sd(insn)) {\n \t\tlen = 8;\n-#endif\n-\t} else if ((insn & INSN_MASK_FSD) == INSN_MATCH_FSD) {\n+\t\trd = riscv_insn_sd_extract_xs2(insn);\n+\t} else if (riscv_insn_is_fsd(insn)) {\n \t\tfp = 1;\n \t\tlen = 8;\n-\t\tval.data_u64 = GET_F64_RS2(insn, regs);\n-\t} else if ((insn & INSN_MASK_FSW) == INSN_MATCH_FSW) {\n+\t\trd = riscv_insn_fsd_extract_fs2(insn);\n+\t} else if (riscv_insn_is_fsw(insn)) {\n \t\tfp = 1;\n \t\tlen = 4;\n-\t\tval.data_ulong = GET_F32_RS2(insn, regs);\n-\t} else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) {\n+\t\trd = riscv_insn_fsw_extract_fs2(insn);\n+\t} else if (riscv_insn_is_sh(insn)) {\n \t\tlen = 2;\n-#if defined(CONFIG_64BIT)\n-\t} else if ((insn & INSN_MASK_C_SD) == INSN_MATCH_C_SD) {\n+\t\trd = riscv_insn_sh_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_sd(insn)) {\n \t\tlen = 8;\n-\t\tval.data_ulong = GET_RS2S(insn, regs);\n-\t} else if ((insn & INSN_MASK_C_SDSP) == INSN_MATCH_C_SDSP) {\n+\t\trd = riscv_insn_c_sd_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_sdsp(insn)) {\n \t\tlen = 8;\n-\t\tval.data_ulong = GET_RS2C(insn, regs);\n-#endif\n-\t} else if ((insn & INSN_MASK_C_SW) == INSN_MATCH_C_SW) {\n+\t\trd = riscv_insn_c_sdsp_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_sw(insn)) {\n \t\tlen = 4;\n-\t\tval.data_ulong = GET_RS2S(insn, regs);\n-\t} else if ((insn & INSN_MASK_C_SWSP) == INSN_MATCH_C_SWSP) {\n+\t\trd = riscv_insn_c_sw_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_swsp(insn)) {\n \t\tlen = 4;\n-\t\tval.data_ulong = GET_RS2C(insn, regs);\n-\t} else if ((insn & INSN_MASK_C_FSD) == INSN_MATCH_C_FSD) {\n+\t\trd = riscv_insn_c_swsp_extract_xs2(insn);\n+\t} else if (riscv_insn_is_c_fsd(insn)) {\n \t\tfp = 1;\n \t\tlen = 8;\n-\t\tval.data_u64 = GET_F64_RS2S(insn, regs);\n-\t} else if ((insn & INSN_MASK_C_FSDSP) == INSN_MATCH_C_FSDSP) {\n+\t\trd = riscv_insn_c_fsd_extract_fs2(insn);\n+\t} else if (riscv_insn_is_c_fsdsp(insn)) {\n \t\tfp = 1;\n \t\tlen = 8;\n-\t\tval.data_u64 = GET_F64_RS2C(insn, regs);\n-#if !defined(CONFIG_64BIT)\n-\t} else if ((insn & INSN_MASK_C_FSW) == INSN_MATCH_C_FSW) {\n+\t\trd = riscv_insn_c_fsdsp_extract_fs2(insn);\n+\t} else if (riscv_insn_is_c_fsw(insn)) {\n \t\tfp = 1;\n \t\tlen = 4;\n-\t\tval.data_ulong = GET_F32_RS2S(insn, regs);\n-\t} else if ((insn & INSN_MASK_C_FSWSP) == INSN_MATCH_C_FSWSP) {\n+\t\trd = riscv_insn_c_fsw_extract_fs2(insn);\n+\t} else if (riscv_insn_is_c_fswsp(insn)) {\n \t\tfp = 1;\n \t\tlen = 4;\n-\t\tval.data_ulong = GET_F32_RS2C(insn, regs);\n-#endif\n-\t} else if ((insn & INSN_MASK_C_SH) == INSN_MATCH_C_SH) {\n+\t\trd = riscv_insn_c_fswsp_extract_fs2(insn);\n+\t} else if (riscv_insn_is_c_sh(insn)) {\n \t\tlen = 2;\n-\t\tval.data_ulong = GET_RS2S(insn, regs);\n+\t\trd = riscv_insn_c_sh_extract_xs2(insn);\n \t} else {\n-\t\tregs->epc = epc;\n \t\treturn -1;\n \t}\n \n \tif (!IS_ENABLED(CONFIG_FPU) && fp)\n \t\treturn -EOPNOTSUPP;\n \n+\tif (!fp)\n+\t\tval.data_ulong = *(unsigned long *)((unsigned long *)regs + rd);\n+\telse if (len == 8)\n+\t\tval.data_u64 = get_f64_rs(rd, regs);\n+\telse\n+\t\tval.data_ulong = get_f32_rs(rd, regs);\n+\n \tif (user_mode(regs)) {\n \t\tif (copy_to_user((u8 __user *)addr, &val, len))\n \t\t\treturn -1;\n", "prefixes": [ "06/16" ] }