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GET /api/1.1/patches/2220785/?format=api
{ "id": 2220785, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220785/?format=api", "web_url": "http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260407-riscv_insn_table-v1-4-54b4736a1e77@gmail.com/", "project": { "id": 70, "url": "http://patchwork.ozlabs.org/api/1.1/projects/70/?format=api", "name": "Linux KVM RISC-V", "link_name": "kvm-riscv", "list_id": "kvm-riscv.lists.infradead.org", "list_email": "kvm-riscv@lists.infradead.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260407-riscv_insn_table-v1-4-54b4736a1e77@gmail.com>", "date": "2026-04-08T04:45:52", "name": "[04/16] riscv: kprobes: Use generated instruction headers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3d8aee11aed2e71be07653423539c33410006bb1", "submitter": { "id": 92521, "url": "http://patchwork.ozlabs.org/api/1.1/people/92521/?format=api", "name": "Charlie Jenkins via B4 Relay", "email": "devnull+thecharlesjenkins.gmail.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260407-riscv_insn_table-v1-4-54b4736a1e77@gmail.com/mbox/", "series": [ { "id": 499063, "url": "http://patchwork.ozlabs.org/api/1.1/series/499063/?format=api", "web_url": "http://patchwork.ozlabs.org/project/kvm-riscv/list/?series=499063", "date": "2026-04-08T04:45:48", "name": "riscv: Generate riscv instruction functions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499063/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220785/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220785/checks/", "tags": {}, "headers": { "Return-Path": "\n <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=xG4q5gZF;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=S0qcOGVi;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org;\n envelope-from=kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n [IPv6:2607:7c80:54:3::133])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fr9Wq545zz1xtJ\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 08 Apr 2026 14:46:44 +1000 (AEST)", "from localhost ([::1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wAKoM-00000008EgZ-1ehZ;\n\tWed, 08 Apr 2026 04:46:42 +0000", "from sea.source.kernel.org ([172.234.252.31])\n\tby bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wAKoI-00000008Ea4-0NsG;\n\tWed, 08 Apr 2026 04:46:40 +0000", "from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58])\n\tby sea.source.kernel.org (Postfix) with ESMTP id A881F4454C;\n\tWed, 8 Apr 2026 04:46:36 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPS id 88D84C19425;\n\tWed, 8 Apr 2026 04:46:36 +0000 (UTC)", "from aws-us-west-2-korg-lkml-1.web.codeaurora.org\n (localhost.localdomain [127.0.0.1])\n\tby smtp.lore.kernel.org (Postfix) with ESMTP id 7F3FDFD5F73;\n\tWed, 8 Apr 2026 04:46:36 +0000 (UTC)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help:\n\tList-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:\n\tMessage-Id:MIME-Version:Subject:Date:From:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=2I7gIqoxTXB4LVs6jC4n6Ogo1T4rjv9pJytZ2pRhmno=; b=xG4q5gZFXljLwV\n\tuubYSo7Weng6JtPzLyzcVBGCmAf/0+92xHdDNZoZj4bfFGM7eybC9hmUtxWQe0Vz7Q0p6twSfAJAj\n\tNGwnC+8EzAvZTxH0LcfsuPP0spGN2NPx39atw0lzP2lKMN1BvU9GGhNZVGDEFlZVMuzD7hiAwhQJP\n\tbTm2JN5AqTYRmOb5LrwClVibtIQazDuxGRnCcoZayDqaNTvjd+fLvEaBG1PgCkrjJEWqGnfgObC3S\n\tbV55epbq4BSgUlbrK/fZoMyevrp6Ame8iC3ROXhlQAQU1mmAOJDK3PVZ7onNTQor/W5qielNDw7+r\n\tmQl7mxTMC1Q9XJKphOmg==;", "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775623596;\n\tbh=WXicD/hNpfCw4NB6cXINcHTlbDKL7VCawFxvYvSLarU=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=S0qcOGVi9A+bTJ2mGsCdvuMPeJ4j5tULw57vWVgIMi0NJ6f8dKayDBf4W406Gs487\n\t nGvhB6H3wEycOjOPArhEXI5hdcYhzAfkSrKRbduujePEEfULRwbD9o3hd2/rUa4VQy\n\t 9gN/Mdk4z2Qb2PFGkspHnMJObSPXcJU1ShKnjE943EnhinXRt+sZLvO/YGLTaISd3q\n\t in1kT7loEYAQeGC/vxEpOxp/rCeEKOOLIKU91QbLp6ZblmVl9WOFYFHq81HIJtz0Xt\n\t R6zElaWgwBS/nsHCng7BcPJU2uszPl/DJba0TwpW94iEb7pUMUxIpkxy8HScG4aMVI\n\t B0zQbYkpCwEZA==" ], "From": "Charlie Jenkins via B4 Relay\n <devnull+thecharlesjenkins.gmail.com@kernel.org>", "Date": "Tue, 07 Apr 2026 21:45:52 -0700", "Subject": "[PATCH 04/16] riscv: kprobes: Use generated instruction headers", "MIME-Version": "1.0", "Message-Id": "<20260407-riscv_insn_table-v1-4-54b4736a1e77@gmail.com>", "References": "<20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com>", "In-Reply-To": "<20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com>", "To": "Paul Walmsley <pjw@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>,\n Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup@brainfault.org>,\n Atish Patra <atish.patra@linux.dev>, Conor Dooley <conor@kernel.org>,\n Paolo Bonzini <pbonzini@redhat.com>,\n Andrew Morton <akpm@linux-foundation.org>, Shuah Khan <shuah@kernel.org>", "Cc": "linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,\n kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,\n linux-kselftest@vger.kernel.org,\n Charlie Jenkins <thecharlesjenkins@gmail.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775623594; l=13795;\n i=thecharlesjenkins@gmail.com; s=2026030; h=from:subject:message-id;\n bh=x0ANg2ba9l8Mn4apQlq7H0DQOpx0fCInS1ySm/aUzMQ=;\n b=WTs1MOLPde3fj267jM3YEanDHNNrb028JgS6eq7qaMAYL0Gym+xWHOr165xCcNxQ57MfgaqH5\n Vt1Q7N3e+ibDgXuNY2kBZz6UNFhRCTxbeq1Uaat0ra0CF1Wb6mo8WCy", "X-Developer-Key": "i=thecharlesjenkins@gmail.com; a=ed25519;\n pk=vpF2USrG+aB6CTbSt34rzJKsAVe/l+GAXo1IomCMETk=", "X-Endpoint-Received": "by B4 Relay for thecharlesjenkins@gmail.com/2026030\n with auth_id=663", "X-Original-From": "Charlie Jenkins <thecharlesjenkins@gmail.com>", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20260407_214638_194588_16D40F41 ", "X-CRM114-Status": "GOOD ( 16.55 )", "X-Spam-Score": "-0.0 (/)", "X-Spam-Report": "Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam. The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: From: Charlie Jenkins Migrate the code that is decoding\n instruction\n for the use of kprobes to use the generated instruction headers instead of\n the hand-written instruction functions. With the more granular instruction\n support, split the decoding of branches into their own functions.\n Content analysis details: (-0.0 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 SPF_PASS SPF: sender matches SPF record\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from\n envelope-from domain\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n author's\n domain\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]\n 0.0 RCVD_IN_VALIDITY_CERTIFIED_BLOCKED RBL: ADMINISTRATOR NOTICE: The\n query to Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [172.234.252.31 listed in\n sa-trusted.bondedsender.org]\n 0.0 RCVD_IN_VALIDITY_SAFE_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to\n Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [172.234.252.31 listed in sa-accredit.habeas.com]\n 0.0 RCVD_IN_VALIDITY_RPBL_BLOCKED RBL: ADMINISTRATOR NOTICE: The query to\n Validity was blocked. See\n https://knowledge.validity.com/hc/en-us/articles/20961730681243\n for more information.\n [172.234.252.31 listed in\n bl.score.senderscore.com]\n 2.1 FREEMAIL_FORGED_REPLYTO Freemail in Reply-To, but not From", "X-BeenThere": "kvm-riscv@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<kvm-riscv.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/kvm-riscv>,\n <mailto:kvm-riscv-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/kvm-riscv/>", "List-Post": "<mailto:kvm-riscv@lists.infradead.org>", "List-Help": "<mailto:kvm-riscv-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/kvm-riscv>,\n <mailto:kvm-riscv-request@lists.infradead.org?subject=subscribe>", "Reply-To": "thecharlesjenkins@gmail.com", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"kvm-riscv\" <kvm-riscv-bounces@lists.infradead.org>", "Errors-To": "kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "From: Charlie Jenkins <thecharlesjenkins@gmail.com>\n\nMigrate the code that is decoding instruction for the use of kprobes to\nuse the generated instruction headers instead of the hand-written\ninstruction functions.\n\nWith the more granular instruction support, split the decoding of branches into\ntheir own functions.\n\nSigned-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com>\n\n---\n\nThis was again verified by checking all 32-bit values for each of these\nfunctions and checking that the two version have the same behavior.\n---\n arch/riscv/include/asm/insn.h | 7 +\n arch/riscv/kernel/probes/decode-insn.c | 7 +-\n arch/riscv/kernel/probes/simulate-insn.c | 253 +++++++++++--------------------\n arch/riscv/kernel/probes/simulate-insn.h | 7 +-\n 4 files changed, 109 insertions(+), 165 deletions(-)", "diff": "diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h\nindex c808e1e15192..43440edc6f1d 100644\n--- a/arch/riscv/include/asm/insn.h\n+++ b/arch/riscv/include/asm/insn.h\n@@ -520,6 +520,13 @@ static inline unsigned long riscv_insn_reg_get_val(unsigned long *regs, u32 inde\n \treturn index ? *(regs + index) : 0;\n }\n \n+static inline void riscv_insn_reg_set_val(unsigned long *regs, u32 index, unsigned long val)\n+{\n+\t/* register 0 is always 0 and not stored in the register struct */\n+\tif (index != 0)\n+\t\t*(regs + index) = val;\n+}\n+\n #define riscv_insn_branch(_insn, regs_ptr, _opcode, _pc, _comparison, type) \\\n \t({ \\\n \t\tunsigned long _ret; \\\ndiff --git a/arch/riscv/kernel/probes/decode-insn.c b/arch/riscv/kernel/probes/decode-insn.c\nindex 65d9590bfb9f..0d70c8301a45 100644\n--- a/arch/riscv/kernel/probes/decode-insn.c\n+++ b/arch/riscv/kernel/probes/decode-insn.c\n@@ -42,7 +42,12 @@ riscv_probe_decode_insn(probe_opcode_t *addr, struct arch_probe_insn *api)\n \tRISCV_INSN_SET_SIMULATE(jal,\t\tinsn);\n \tRISCV_INSN_SET_SIMULATE(jalr,\t\tinsn);\n \tRISCV_INSN_SET_SIMULATE(auipc,\t\tinsn);\n-\tRISCV_INSN_SET_SIMULATE(branch,\t\tinsn);\n+\tRISCV_INSN_SET_SIMULATE(beq,\t\tinsn);\n+\tRISCV_INSN_SET_SIMULATE(bne,\t\tinsn);\n+\tRISCV_INSN_SET_SIMULATE(blt,\t\tinsn);\n+\tRISCV_INSN_SET_SIMULATE(bge,\t\tinsn);\n+\tRISCV_INSN_SET_SIMULATE(bltu,\t\tinsn);\n+\tRISCV_INSN_SET_SIMULATE(bgeu,\t\tinsn);\n \n \treturn INSN_GOOD;\n }\ndiff --git a/arch/riscv/kernel/probes/simulate-insn.c b/arch/riscv/kernel/probes/simulate-insn.c\nindex fa581590c1f8..d086d3c6474c 100644\n--- a/arch/riscv/kernel/probes/simulate-insn.c\n+++ b/arch/riscv/kernel/probes/simulate-insn.c\n@@ -4,236 +4,163 @@\n #include <linux/kernel.h>\n #include <linux/kprobes.h>\n \n-#include \"decode-insn.h\"\n+#include <asm/insn.h>\n #include \"simulate-insn.h\"\n \n-static inline bool rv_insn_reg_get_val(struct pt_regs *regs, u32 index,\n-\t\t\t\t unsigned long *ptr)\n-{\n-\tif (index == 0)\n-\t\t*ptr = 0;\n-\telse if (index <= 31)\n-\t\t*ptr = *((unsigned long *)regs + index);\n-\telse\n-\t\treturn false;\n-\n-\treturn true;\n-}\n-\n-static inline bool rv_insn_reg_set_val(struct pt_regs *regs, u32 index,\n-\t\t\t\t unsigned long val)\n-{\n-\tif (index == 0)\n-\t\treturn true;\n-\telse if (index <= 31)\n-\t\t*((unsigned long *)regs + index) = val;\n-\telse\n-\t\treturn false;\n-\n-\treturn true;\n-}\n-\n bool __kprobes simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\t/*\n-\t * 31 30 21 20 19 12 11 7 6 0\n-\t * imm [20] | imm[10:1] | imm[11] | imm[19:12] | rd | opcode\n-\t * 1 10 1 8 5 JAL/J\n-\t */\n-\tbool ret;\n-\ts32 imm;\n-\tu32 index = RV_EXTRACT_RD_REG(opcode);\n+\ts32 imm = riscv_insn_jal_extract_imm(opcode);\n+\tu32 index = riscv_insn_jal_extract_xd(opcode);\n \n-\tret = rv_insn_reg_set_val(regs, index, addr + 4);\n-\tif (!ret)\n-\t\treturn ret;\n-\n-\timm = RV_EXTRACT_JTYPE_IMM(opcode);\n+\triscv_insn_reg_set_val((unsigned long *)regs, index, addr + 4);\n \n \tinstruction_pointer_set(regs, addr + imm);\n \n-\treturn ret;\n+\treturn true;\n }\n \n bool __kprobes simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\t/*\n-\t * 31 20 19 15 14 12 11 7 6 0\n-\t * offset[11:0] | rs1 | 010 | rd | opcode\n-\t * 12 5 3 5 JALR/JR\n-\t */\n-\tbool ret;\n \tunsigned long base_addr;\n-\tu32 imm = RV_EXTRACT_ITYPE_IMM(opcode);\n-\tu32 rd_index = RV_EXTRACT_RD_REG(opcode);\n-\tu32 rs1_index = RV_EXTRACT_RS1_REG(opcode);\n+\ts32 imm = riscv_insn_jalr_extract_imm(opcode);\n+\tu32 rd_index = riscv_insn_jalr_extract_xd(opcode);\n+\tu32 rs1_index = riscv_insn_jalr_extract_xs1(opcode);\n \n-\tret = rv_insn_reg_get_val(regs, rs1_index, &base_addr);\n-\tif (!ret)\n-\t\treturn ret;\n+\tbase_addr = riscv_insn_reg_get_val((unsigned long *)regs, rs1_index);\n \n-\tret = rv_insn_reg_set_val(regs, rd_index, addr + 4);\n-\tif (!ret)\n-\t\treturn ret;\n+\triscv_insn_reg_set_val((unsigned long *)regs, rd_index, addr + 4);\n \n-\tinstruction_pointer_set(regs, (base_addr + sign_extend32((imm), 11))&~1);\n+\tinstruction_pointer_set(regs, (base_addr + imm) & ~1);\n \n-\treturn ret;\n+\treturn true;\n }\n \n bool __kprobes simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\t/*\n-\t * auipc instruction:\n-\t * 31 12 11 7 6 0\n-\t * | imm[31:12] | rd | opcode |\n-\t * 20 5 7\n-\t */\n+\tu32 rd_index = riscv_insn_auipc_extract_xd(opcode);\n+\tunsigned long rd_val = addr + (s32)riscv_insn_auipc_extract_imm(opcode);\n \n-\tu32 rd_idx = RV_EXTRACT_RD_REG(opcode);\n-\tunsigned long rd_val = addr + (s32)RV_EXTRACT_UTYPE_IMM(opcode);\n-\n-\tif (!rv_insn_reg_set_val(regs, rd_idx, rd_val))\n-\t\treturn false;\n+\triscv_insn_reg_set_val((unsigned long *)regs, rd_index, rd_val);\n \n \tinstruction_pointer_set(regs, addr + 4);\n-\n \treturn true;\n }\n \n-bool __kprobes simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+bool __kprobes simulate_beq(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\t/*\n-\t * branch instructions:\n-\t * 31 30 25 24 20 19 15 14 12 11 8 7 6 0\n-\t * | imm[12] | imm[10:5] | rs2 | rs1 | funct3 | imm[4:1] | imm[11] | opcode |\n-\t * 1 6 5 5 3 4 1 7\n-\t * imm[12|10:5] rs2 rs1 000 imm[4:1|11] 1100011 BEQ\n-\t * imm[12|10:5] rs2 rs1 001 imm[4:1|11] 1100011 BNE\n-\t * imm[12|10:5] rs2 rs1 100 imm[4:1|11] 1100011 BLT\n-\t * imm[12|10:5] rs2 rs1 101 imm[4:1|11] 1100011 BGE\n-\t * imm[12|10:5] rs2 rs1 110 imm[4:1|11] 1100011 BLTU\n-\t * imm[12|10:5] rs2 rs1 111 imm[4:1|11] 1100011 BGEU\n-\t */\n-\n-\ts32 offset;\n-\ts32 offset_tmp;\n-\tunsigned long rs1_val;\n-\tunsigned long rs2_val;\n-\n-\tif (!rv_insn_reg_get_val(regs, RV_EXTRACT_RS1_REG(opcode), &rs1_val) ||\n-\t !rv_insn_reg_get_val(regs, RV_EXTRACT_RS2_REG(opcode), &rs2_val))\n-\t\treturn false;\n-\n-\toffset_tmp = RV_EXTRACT_BTYPE_IMM(opcode);\n-\tswitch (RV_EXTRACT_FUNCT3(opcode)) {\n-\tcase RVG_FUNCT3_BEQ:\n-\t\toffset = (rs1_val == rs2_val) ? offset_tmp : 4;\n-\t\tbreak;\n-\tcase RVG_FUNCT3_BNE:\n-\t\toffset = (rs1_val != rs2_val) ? offset_tmp : 4;\n-\t\tbreak;\n-\tcase RVG_FUNCT3_BLT:\n-\t\toffset = ((long)rs1_val < (long)rs2_val) ? offset_tmp : 4;\n-\t\tbreak;\n-\tcase RVG_FUNCT3_BGE:\n-\t\toffset = ((long)rs1_val >= (long)rs2_val) ? offset_tmp : 4;\n-\t\tbreak;\n-\tcase RVG_FUNCT3_BLTU:\n-\t\toffset = (rs1_val < rs2_val) ? offset_tmp : 4;\n-\t\tbreak;\n-\tcase RVG_FUNCT3_BGEU:\n-\t\toffset = (rs1_val >= rs2_val) ? offset_tmp : 4;\n-\t\tbreak;\n-\tdefault:\n-\t\treturn false;\n-\t}\n-\n-\tinstruction_pointer_set(regs, addr + offset);\n+\tunsigned long next_addr;\n \n+\tnext_addr = riscv_insn_branch(beq, (unsigned long *)regs, opcode, addr, ==, unsigned long);\n+\tinstruction_pointer_set(regs, next_addr);\n \treturn true;\n }\n \n-bool __kprobes simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+bool __kprobes simulate_bne(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\ts32 offset = RVC_EXTRACT_JTYPE_IMM(opcode);\n+\tunsigned long next_addr;\n \n-\tinstruction_pointer_set(regs, addr + offset);\n+\tnext_addr = riscv_insn_branch(bne, (unsigned long *)regs, opcode, addr, !=, unsigned long);\n+\tinstruction_pointer_set(regs, next_addr);\n+\treturn true;\n+}\n \n+bool __kprobes simulate_blt(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+{\n+\tunsigned long next_addr;\n+\n+\tnext_addr = riscv_insn_branch(blt, (unsigned long *)regs, opcode, addr, <, long);\n+\tinstruction_pointer_set(regs, next_addr);\n \treturn true;\n }\n \n-static bool __kprobes simulate_c_jr_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs,\n-\t\t\t\t\t bool is_jalr)\n+bool __kprobes simulate_bge(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\t/*\n-\t * 15 12 11 7 6 2 1 0\n-\t * | funct4 | rs1 | rs2 | op |\n-\t * 4 5 5 2\n-\t */\n+\tunsigned long next_addr;\n \n-\tunsigned long jump_addr;\n+\tnext_addr = riscv_insn_branch(bge, (unsigned long *)regs, opcode, addr, >=, long);\n+\tinstruction_pointer_set(regs, next_addr);\n+\treturn true;\n+}\n \n-\tu32 rs1 = RVC_EXTRACT_C2_RS1_REG(opcode);\n+bool __kprobes simulate_bltu(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+{\n+\tunsigned long next_addr;\n \n-\tif (rs1 == 0) /* C.JR is only valid when rs1 != x0 */\n-\t\treturn false;\n+\tnext_addr = riscv_insn_branch(bltu, (unsigned long *)regs, opcode, addr, <, unsigned long);\n+\tinstruction_pointer_set(regs, next_addr);\n+\treturn true;\n+}\n \n-\tif (!rv_insn_reg_get_val(regs, rs1, &jump_addr))\n-\t\treturn false;\n+bool __kprobes simulate_bgeu(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+{\n+\tunsigned long next_addr;\n+\n+\tnext_addr = riscv_insn_branch(bgeu, (unsigned long *)regs, opcode, addr, >=, unsigned long);\n+\tinstruction_pointer_set(regs, next_addr);\n+\treturn true;\n+}\n \n-\tif (is_jalr && !rv_insn_reg_set_val(regs, 1, addr + 2))\n-\t\treturn false;\n+bool __kprobes simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs)\n+{\n+\ts32 offset = riscv_insn_c_j_extract_imm(opcode);\n \n-\tinstruction_pointer_set(regs, jump_addr);\n+\tinstruction_pointer_set(regs, addr + offset);\n \n \treturn true;\n }\n \n bool __kprobes simulate_c_jr(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\treturn simulate_c_jr_jalr(opcode, addr, regs, false);\n+\tunsigned long next_addr;\n+\tunsigned long *regs_ptr = (unsigned long *)regs;\n+\n+\tnext_addr = regs_ptr[riscv_insn_c_jr_extract_xs1(opcode)];\n+\tinstruction_pointer_set(regs, next_addr);\n+\n+\tregs->ra = addr + 2;\n+\treturn true;\n }\n \n bool __kprobes simulate_c_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\treturn simulate_c_jr_jalr(opcode, addr, regs, true);\n+\tunsigned long next_addr;\n+\tunsigned long *regs_ptr = (unsigned long *)regs;\n+\n+\tnext_addr = regs_ptr[riscv_insn_c_jalr_extract_xs1(opcode)];\n+\tinstruction_pointer_set(regs, next_addr);\n+\n+\tregs->ra = addr + 2;\n+\treturn true;\n }\n \n-static bool __kprobes simulate_c_bnez_beqz(u32 opcode, unsigned long addr, struct pt_regs *regs,\n-\t\t\t\t\t bool is_bnez)\n+bool __kprobes simulate_c_bnez(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\t/*\n-\t * 15 13 12 10 9 7 6 2 1 0\n-\t * | funct3 | offset[8|4:3] | rs1' | offset[7:6|2:1|5] | op |\n-\t * 3 3 3 5 2\n-\t */\n-\n-\ts32 offset;\n \tu32 rs1;\n-\tunsigned long rs1_val;\n+\tunsigned long offset;\n+\tunsigned long *regs_ptr = (unsigned long *)regs;\n \n-\trs1 = 0x8 | ((opcode >> 7) & 0x7);\n-\n-\tif (!rv_insn_reg_get_val(regs, rs1, &rs1_val))\n-\t\treturn false;\n-\n-\tif ((rs1_val != 0 && is_bnez) || (rs1_val == 0 && !is_bnez))\n-\t\toffset = RVC_EXTRACT_BTYPE_IMM(opcode);\n+\trs1 = riscv_insn_c_bnez_extract_xs1(opcode);\n+\tif (regs_ptr[8 + rs1] != 0)\n+\t\toffset = riscv_insn_c_bnez_extract_imm(opcode);\n \telse\n \t\toffset = 2;\n \n \tinstruction_pointer_set(regs, addr + offset);\n-\n \treturn true;\n }\n \n-bool __kprobes simulate_c_bnez(u32 opcode, unsigned long addr, struct pt_regs *regs)\n-{\n-\treturn simulate_c_bnez_beqz(opcode, addr, regs, true);\n-}\n-\n bool __kprobes simulate_c_beqz(u32 opcode, unsigned long addr, struct pt_regs *regs)\n {\n-\treturn simulate_c_bnez_beqz(opcode, addr, regs, false);\n+\tu32 rs1;\n+\tunsigned long offset;\n+\tunsigned long *regs_ptr = (unsigned long *)regs;\n+\n+\trs1 = riscv_insn_c_beqz_extract_xs1(opcode);\n+\tif (regs_ptr[8 + rs1] == 0)\n+\t\toffset = riscv_insn_c_beqz_extract_imm(opcode);\n+\telse\n+\t\toffset = 2;\n+\n+\tinstruction_pointer_set(regs, addr + offset);\n+\treturn true;\n }\ndiff --git a/arch/riscv/kernel/probes/simulate-insn.h b/arch/riscv/kernel/probes/simulate-insn.h\nindex 44ebbc444db9..f2f707e92dee 100644\n--- a/arch/riscv/kernel/probes/simulate-insn.h\n+++ b/arch/riscv/kernel/probes/simulate-insn.h\n@@ -21,7 +21,12 @@\n \t} while (0)\n \n bool simulate_auipc(u32 opcode, unsigned long addr, struct pt_regs *regs);\n-bool simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs);\n+bool simulate_beq(u32 opcode, unsigned long addr, struct pt_regs *regs);\n+bool simulate_bne(u32 opcode, unsigned long addr, struct pt_regs *regs);\n+bool simulate_blt(u32 opcode, unsigned long addr, struct pt_regs *regs);\n+bool simulate_bge(u32 opcode, unsigned long addr, struct pt_regs *regs);\n+bool simulate_bltu(u32 opcode, unsigned long addr, struct pt_regs *regs);\n+bool simulate_bgeu(u32 opcode, unsigned long addr, struct pt_regs *regs);\n bool simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs);\n bool simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);\n bool simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs);\n", "prefixes": [ "04/16" ] }