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GET /api/1.1/patches/2220782/?format=api
{ "id": 2220782, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220782/?format=api", "web_url": "http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260407-riscv_insn_table-v1-2-54b4736a1e77@gmail.com/", "project": { "id": 70, "url": "http://patchwork.ozlabs.org/api/1.1/projects/70/?format=api", "name": "Linux KVM RISC-V", "link_name": "kvm-riscv", "list_id": "kvm-riscv.lists.infradead.org", "list_email": "kvm-riscv@lists.infradead.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260407-riscv_insn_table-v1-2-54b4736a1e77@gmail.com>", "date": "2026-04-08T04:45:50", "name": "[02/16] riscv: alternatives: Use generated instruction headers for patching code", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "00b2a6205cdc052d9cbc447156606aa5ab617176", "submitter": { "id": 92521, "url": "http://patchwork.ozlabs.org/api/1.1/people/92521/?format=api", "name": "Charlie Jenkins via B4 Relay", "email": "devnull+thecharlesjenkins.gmail.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260407-riscv_insn_table-v1-2-54b4736a1e77@gmail.com/mbox/", "series": [ { "id": 499063, "url": "http://patchwork.ozlabs.org/api/1.1/series/499063/?format=api", "web_url": "http://patchwork.ozlabs.org/project/kvm-riscv/list/?series=499063", "date": "2026-04-08T04:45:48", "name": "riscv: Generate riscv instruction functions", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499063/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220782/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220782/checks/", "tags": {}, "headers": { "Return-Path": "\n <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=fyS4VBsX;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=kv/VIE24;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; helo=bombadil.infradead.org;\n envelope-from=kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n [IPv6:2607:7c80:54:3::133])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fr9Wr2Lfhz211M\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 08 Apr 2026 14:46:45 +1000 (AEST)", "from localhost ([::1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wAKoI-00000008Eb7-3Sbr;\n\tWed, 08 Apr 2026 04:46:38 +0000", "from tor.source.kernel.org ([172.105.4.254])\n\tby bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux))\n\tid 1wAKoH-00000008Ea3-2kUt;\n\tWed, 08 Apr 2026 04:46:37 +0000", "from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58])\n\tby tor.source.kernel.org (Postfix) with ESMTP id AD82A60139;\n\tWed, 8 Apr 2026 04:46:36 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPS id 59833C2BCB1;\n\tWed, 8 Apr 2026 04:46:36 +0000 (UTC)", "from aws-us-west-2-korg-lkml-1.web.codeaurora.org\n (localhost.localdomain [127.0.0.1])\n\tby smtp.lore.kernel.org (Postfix) with ESMTP id 51006FD5F70;\n\tWed, 8 Apr 2026 04:46:36 +0000 (UTC)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20210309; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Reply-To:List-Subscribe:List-Help:\n\tList-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References:\n\tMessage-Id:MIME-Version:Subject:Date:From:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=66f4v+sQ42CHwQ8zAbHFeKmT09b+PfiA/USfxN96q/E=; b=fyS4VBsX4KJDt2\n\t9deII7kMTI7wqH8dRjW2kpmpWyMzP9PjuFtoHNcmVevATRgDuVbI31I+Q8glCmCGymBfLKf6taUMv\n\tjbwcLmiOMZXb+TjbWCYCrGesN+s+8bL5GS3t2yzTnD5K+mH9IyJ2frWyN8kLfGVH3efG0n1lURos6\n\tBqSrubh5G50amONMJdNCW6zUHcNaQfVAuoRjEC7eSz0++al9uffiyMcj3KIF1cApQv79nLYi9a3T5\n\tIx9APHm/qG4eiXLhf5eGQRk6KqZJFTgWO1GSwTVyz6ZwG9m6H7w3XQi3JZVNHEUCaGU0gRySr0sIb\n\tt3DkwOZcV9Twh86Ql88Q==;", "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775623596;\n\tbh=m0dL3yAYZBo0Ax2wYzAYaVBbrxY2QN9Hxv/9SE5tFGY=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=kv/VIE24QHxEqDoJvqHVV/om+O7OBCFjULsoUbBqrmj+i2EXIalq72/62E1eXawu3\n\t AhgIbHmao776Qu2iISaPLoyesEqxREI/5egAQMcfuawwotFdH6ybF2ct5sSp6T709P\n\t 6yKI4VXzG75qZELMTtroRpAdHX9F4cYpFZhs8gW/y0Lxyk97kGEvt1jNKvVC08NXPz\n\t /qYqZQgCpc1z/TIGPlmyxK7uKiJmj9bmNcZClWkqZQup7ZNxeaTx0fcIYhQgK5Lrrp\n\t mZ+ExWg1ipa0fqI097qoulUDwVxicd3Nvj3pmcTL3wXZe01y1C6h1GBhEFiQoQnw+S\n\t 6kdTVs4kOoEVA==" ], "From": "Charlie Jenkins via B4 Relay\n <devnull+thecharlesjenkins.gmail.com@kernel.org>", "Date": "Tue, 07 Apr 2026 21:45:50 -0700", "Subject": "[PATCH 02/16] riscv: alternatives: Use generated instruction\n headers for patching code", "MIME-Version": "1.0", "Message-Id": "<20260407-riscv_insn_table-v1-2-54b4736a1e77@gmail.com>", "References": "<20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com>", "In-Reply-To": "<20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com>", "To": "Paul Walmsley <pjw@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>,\n Alexandre Ghiti <alex@ghiti.fr>, Anup Patel <anup@brainfault.org>,\n Atish Patra <atish.patra@linux.dev>, Conor Dooley <conor@kernel.org>,\n Paolo Bonzini <pbonzini@redhat.com>,\n Andrew Morton <akpm@linux-foundation.org>, Shuah Khan <shuah@kernel.org>", "Cc": "linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,\n kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,\n linux-kselftest@vger.kernel.org,\n Charlie Jenkins <thecharlesjenkins@gmail.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775623594; l=7576;\n i=thecharlesjenkins@gmail.com; s=2026030; h=from:subject:message-id;\n bh=JXCpev2GGkdP2+kuuGxKizLYqir1lPNREbstw34ToJM=;\n b=6q4DOCxE9sLo80b7JYetbMtU5or5ZBqteeBHI2mFsiqGtLpaJqFo5BUe4eI6FgA26GZtvU+Fr\n vQrx97MDhwtCnXyonXn7V5FYkLE/CXQ832/D6lHjVuv1JiWHyKE+Da/", "X-Developer-Key": "i=thecharlesjenkins@gmail.com; a=ed25519;\n pk=vpF2USrG+aB6CTbSt34rzJKsAVe/l+GAXo1IomCMETk=", "X-Endpoint-Received": "by B4 Relay for thecharlesjenkins@gmail.com/2026030\n with auth_id=663", "X-Original-From": "Charlie Jenkins <thecharlesjenkins@gmail.com>", "X-BeenThere": "kvm-riscv@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<kvm-riscv.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/kvm-riscv>,\n <mailto:kvm-riscv-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/kvm-riscv/>", "List-Post": "<mailto:kvm-riscv@lists.infradead.org>", "List-Help": "<mailto:kvm-riscv-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/kvm-riscv>,\n <mailto:kvm-riscv-request@lists.infradead.org?subject=subscribe>", "Reply-To": "thecharlesjenkins@gmail.com", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"kvm-riscv\" <kvm-riscv-bounces@lists.infradead.org>", "Errors-To": "kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "From: Charlie Jenkins <thecharlesjenkins@gmail.com>\n\nMigrate the alternatives patching code to use the generated instruction\nheaders instead of the hand-written instruction composition functions.\n\nSigned-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com>\n\n---\n\nThese function expansions are very simple and almost expand to the same\nthing in the new and old version. The main difference is\nriscv_insn_auipc_extract_imm() in the new version expands to:\n\n((_insn >> 12 & GENMASK(19, 0)) << 12)\n\nwhile it expands to the following in the old version:\n\n((_insn >> 0) & GENMASK(31, 12))\n\nThese are the same thing, but GCC is unable to properly optimize the\nsecond one so the first one ends up using almost half as many\ninstructions. With this finding and other similar examples, I made\nthe generated headers construct in the first way to help GCC optimize\nall of these functions.\n\nBrute force can also be checked with this code:\n\nvoid check_auipc_jalr() {\n\tfor (unsigned int auipc = 0; auipc < ((1ULL << 12) - 1); auipc++) {\n\t\tfor (unsigned int jalr = 0; jalr < ((1ULL << 20) - 1); jalr++) {\n\t\t\tunsigned int auipc_t=riscv_insn_auipc(auipc, 0), jalr_t=riscv_insn_jalr(jalr, 0, 0), auipc_t2=riscv_insn_auipc(auipc, 0), jalr_t2=riscv_insn_jalr(jalr, 0, 0);\n\t\t\triscv_alternative_fix_auipc_jalr(&auipc_t, &jalr_t, 0);\n\t\t\triscv_alternative_fix_auipc_jalr2(&auipc_t2, &jalr_t2, 0);\n\n\t\t\tif (auipc_t != auipc_t2) {\n\t\t\t\tprintf(\"auipcs don't match %u, %u: %u != %u\\n\", auipc, jalr, auipc_t, auipc_t2);\n\t\t\t\treturn;\n\t\t\t}\n\n\t\t\tif (jalr_t != jalr_t2) {\n\t\t\t\tprintf(\"jalrs don't match %u: %u != %u\\n\", i, jalr_t, jalr_t2);\n\t\t\t}\n\t\t}\n\t}\n}\n---\n arch/riscv/include/asm/insn.h | 74 -----------------------------------------\n arch/riscv/kernel/alternative.c | 23 +++++++++----\n 2 files changed, 17 insertions(+), 80 deletions(-)", "diff": "diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h\nindex d562b2b40ba1..d0e137f9bcd7 100644\n--- a/arch/riscv/include/asm/insn.h\n+++ b/arch/riscv/include/asm/insn.h\n@@ -514,78 +514,4 @@ static __always_inline bool riscv_insn_is_branch(u32 code)\n \n #define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)\n \n-/*\n- * Get the immediate from a J-type instruction.\n- *\n- * @insn: instruction to process\n- * Return: immediate\n- */\n-static inline s32 riscv_insn_extract_jtype_imm(u32 insn)\n-{\n-\treturn RV_EXTRACT_JTYPE_IMM(insn);\n-}\n-\n-/*\n- * Update a J-type instruction with an immediate value.\n- *\n- * @insn: pointer to the jtype instruction\n- * @imm: the immediate to insert into the instruction\n- */\n-static inline void riscv_insn_insert_jtype_imm(u32 *insn, s32 imm)\n-{\n-\t/* drop the old IMMs, all jal IMM bits sit at 31:12 */\n-\t*insn &= ~GENMASK(31, 12);\n-\t*insn |= (RV_X_MASK(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) |\n-\t\t (RV_X_MASK(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) |\n-\t\t (RV_X_MASK(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) |\n-\t\t (RV_X_MASK(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF);\n-}\n-\n-/*\n- * Put together one immediate from a U-type and I-type instruction pair.\n- *\n- * The U-type contains an upper immediate, meaning bits[31:12] with [11:0]\n- * being zero, while the I-type contains a 12bit immediate.\n- * Combined these can encode larger 32bit values and are used for example\n- * in auipc + jalr pairs to allow larger jumps.\n- *\n- * @utype_insn: instruction containing the upper immediate\n- * @itype_insn: instruction\n- * Return: combined immediate\n- */\n-static inline s32 riscv_insn_extract_utype_itype_imm(u32 utype_insn, u32 itype_insn)\n-{\n-\ts32 imm;\n-\n-\timm = RV_EXTRACT_UTYPE_IMM(utype_insn);\n-\timm += RV_EXTRACT_ITYPE_IMM(itype_insn);\n-\n-\treturn imm;\n-}\n-\n-/*\n- * Update a set of two instructions (U-type + I-type) with an immediate value.\n- *\n- * Used for example in auipc+jalrs pairs the U-type instructions contains\n- * a 20bit upper immediate representing bits[31:12], while the I-type\n- * instruction contains a 12bit immediate representing bits[11:0].\n- *\n- * This also takes into account that both separate immediates are\n- * considered as signed values, so if the I-type immediate becomes\n- * negative (BIT(11) set) the U-type part gets adjusted.\n- *\n- * @utype_insn: pointer to the utype instruction of the pair\n- * @itype_insn: pointer to the itype instruction of the pair\n- * @imm: the immediate to insert into the two instructions\n- */\n-static inline void riscv_insn_insert_utype_itype_imm(u32 *utype_insn, u32 *itype_insn, s32 imm)\n-{\n-\t/* drop possible old IMM values */\n-\t*utype_insn &= ~(RV_U_IMM_31_12_MASK);\n-\t*itype_insn &= ~(RV_I_IMM_11_0_MASK << RV_I_IMM_11_0_OPOFF);\n-\n-\t/* add the adapted IMMs */\n-\t*utype_insn |= (imm & RV_U_IMM_31_12_MASK) + ((imm & BIT(11)) << 1);\n-\t*itype_insn |= ((imm & RV_I_IMM_11_0_MASK) << RV_I_IMM_11_0_OPOFF);\n-}\n #endif /* _ASM_RISCV_INSN_H */\ndiff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c\nindex 7642704c7f18..b26a90eb65cc 100644\n--- a/arch/riscv/kernel/alternative.c\n+++ b/arch/riscv/kernel/alternative.c\n@@ -11,6 +11,7 @@\n #include <linux/cpu.h>\n #include <linux/uaccess.h>\n #include <asm/alternative.h>\n+#include <asm/insn.h>\n #include <asm/module.h>\n #include <asm/sections.h>\n #include <asm/vdso.h>\n@@ -78,14 +79,24 @@ static void riscv_alternative_fix_auipc_jalr(void *ptr, u32 auipc_insn,\n \t\t\t\t\t u32 jalr_insn, int patch_offset)\n {\n \tu32 call[2] = { auipc_insn, jalr_insn };\n+\tu32 auipc_imm;\n \ts32 imm;\n \n \t/* get and adjust new target address */\n-\timm = riscv_insn_extract_utype_itype_imm(auipc_insn, jalr_insn);\n+\timm = riscv_insn_auipc_extract_imm(auipc_insn) + riscv_insn_jalr_extract_imm(jalr_insn);\n \timm -= patch_offset;\n \n+\t/*\n+\t * When the 32-bit immediate is split across auipc and jalr, the\n+\t * constructed immediates need to be treated as individually sign\n+\t * extended numbers. Add the sign bit of the lower 12 bits to the upper\n+\t * 20 bits to undo the bleeding of the sign.\n+\t */\n+\tauipc_imm = imm + (BIT(11) << 1);\n+\n \t/* update instructions */\n-\triscv_insn_insert_utype_itype_imm(&call[0], &call[1], imm);\n+\triscv_insn_auipc_insert_imm(&call[0], auipc_imm);\n+\triscv_insn_jalr_insert_imm(&call[1], imm);\n \n \t/* patch the call place again */\n \tpatch_text_nosync(ptr, call, sizeof(u32) * 2);\n@@ -96,11 +107,11 @@ static void riscv_alternative_fix_jal(void *ptr, u32 jal_insn, int patch_offset)\n \ts32 imm;\n \n \t/* get and adjust new target address */\n-\timm = riscv_insn_extract_jtype_imm(jal_insn);\n+\timm = riscv_insn_jal_extract_imm(jal_insn);\n \timm -= patch_offset;\n \n \t/* update instruction */\n-\triscv_insn_insert_jtype_imm(&jal_insn, imm);\n+\triscv_insn_jal_insert_imm(&jal_insn, imm);\n \n \t/* patch the call place again */\n \tpatch_text_nosync(ptr, &jal_insn, sizeof(u32));\n@@ -127,7 +138,7 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsigned int len,\n \t\t\t\tcontinue;\n \n \t\t\t/* if instruction pair is a call, it will use the ra register */\n-\t\t\tif (RV_EXTRACT_RD_REG(insn) != 1)\n+\t\t\tif (riscv_insn_jalr_extract_xd(insn) != 1)\n \t\t\t\tcontinue;\n \n \t\t\triscv_alternative_fix_auipc_jalr(alt_ptr + i * sizeof(u32),\n@@ -136,7 +147,7 @@ void riscv_alternative_fix_offsets(void *alt_ptr, unsigned int len,\n \t\t}\n \n \t\tif (riscv_insn_is_jal(insn)) {\n-\t\t\ts32 imm = riscv_insn_extract_jtype_imm(insn);\n+\t\t\ts32 imm = riscv_insn_jal_extract_imm(insn);\n \n \t\t\t/* Don't modify jumps inside the alternative block */\n \t\t\tif ((alt_ptr + i * sizeof(u32) + imm) >= alt_ptr &&\n", "prefixes": [ "02/16" ] }