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GET /api/1.1/patches/2220652/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2220652,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220652/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407151707.46536-10-mohamed@unpredictable.fr/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260407151707.46536-10-mohamed@unpredictable.fr>",
    "date": "2026-04-07T15:17:03",
    "name": "[v9,09/13] whpx: i386: use WHvX64RegisterCr8 only when kernel-irqchip=off",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "fdf8a7880917f8e1e26cefbbd6846b1aeb98968d",
    "submitter": {
        "id": 91318,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/91318/?format=api",
        "name": "Mohamed Mediouni",
        "email": "mohamed@unpredictable.fr"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260407151707.46536-10-mohamed@unpredictable.fr/mbox/",
    "series": [
        {
            "id": 499027,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/499027/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499027",
            "date": "2026-04-07T15:17:06",
            "name": "whpx: i386: bug fixes, feature probing and CPUID",
            "version": 9,
            "mbox": "http://patchwork.ozlabs.org/series/499027/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2220652/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2220652/checks/",
    "tags": {},
    "headers": {
        "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>",
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        ],
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        "mail-alias-created-date": "1752046281608",
        "From": "Mohamed Mediouni <mohamed@unpredictable.fr>",
        "To": "qemu-devel@nongnu.org",
        "Cc": "Phil Dennis-Jordan <phil@philjordan.eu>,\n Paolo Bonzini <pbonzini@redhat.com>,\n Mohamed Mediouni <mohamed@unpredictable.fr>,\n Zhao Liu <zhao1.liu@intel.com>, Pedro Barbuda <pbarbuda@microsoft.com>,\n Roman Bolshakov <rbolshakov@ddn.com>, Wei Liu <wei.liu@kernel.org>",
        "Subject": "[PATCH v9 09/13] whpx: i386: use WHvX64RegisterCr8 only when\n kernel-irqchip=off",
        "Date": "Tue,  7 Apr 2026 17:17:03 +0200",
        "Message-ID": "<20260407151707.46536-10-mohamed@unpredictable.fr>",
        "X-Mailer": "git-send-email 2.50.1",
        "In-Reply-To": "<20260407151707.46536-1-mohamed@unpredictable.fr>",
        "References": "<20260407151707.46536-1-mohamed@unpredictable.fr>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
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        "X-Spam_bar": "--",
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        "List-Id": "qemu development <qemu-devel.nongnu.org>",
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    },
    "content": "When kernel-irqchip=on, manage TPR as part of the APIC state instead entirely.\n\nThis fixes some failure to set state errors.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\n---\n target/i386/whpx/whpx-all.c | 37 ++++++++++++++++++++++---------------\n 1 file changed, 22 insertions(+), 15 deletions(-)",
    "diff": "diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c\nindex 62542922a4..74b94b799e 100644\n--- a/target/i386/whpx/whpx-all.c\n+++ b/target/i386/whpx/whpx-all.c\n@@ -95,7 +95,6 @@ static const WHV_REGISTER_NAME whpx_register_names[] = {\n     WHvX64RegisterCr2,\n     WHvX64RegisterCr3,\n     WHvX64RegisterCr4,\n-    WHvX64RegisterCr8,\n \n     /* X64 Debug Registers */\n     /*\n@@ -459,8 +458,11 @@ void whpx_set_registers(CPUState *cpu, WHPXStateLevel level)\n         vcxt.values[idx++].Reg64 = env->cr[3];\n         assert(whpx_register_names[idx] == WHvX64RegisterCr4);\n         vcxt.values[idx++].Reg64 = env->cr[4];\n-        assert(whpx_register_names[idx] == WHvX64RegisterCr8);\n-        vcxt.values[idx++].Reg64 = vcpu->tpr;\n+        /* For kernel-irqchip=on, TPR is managed as part of APIC state */\n+        if (!whpx_irqchip_in_kernel()) {\n+            WHV_REGISTER_VALUE cr8 = {.Reg64 = vcpu->tpr};\n+            whpx_set_reg(cpu, WHvX64RegisterCr8, cr8);\n+        }\n \n         /* 8 Debug Registers - Skipped */\n \n@@ -716,11 +718,14 @@ void whpx_get_registers(CPUState *cpu, WHPXStateLevel level)\n     env->cr[3] = vcxt.values[idx++].Reg64;\n     assert(whpx_register_names[idx] == WHvX64RegisterCr4);\n     env->cr[4] = vcxt.values[idx++].Reg64;\n-    assert(whpx_register_names[idx] == WHvX64RegisterCr8);\n-    tpr = vcxt.values[idx++].Reg64;\n-    if (tpr != vcpu->tpr) {\n-        vcpu->tpr = tpr;\n-        cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n+\n+    /* For kernel-irqchip=on, TPR is managed as part of APIC state */\n+    if (!whpx_irqchip_in_kernel()) {\n+        tpr = vcpu->exit_ctx.VpContext.Cr8;\n+        if (tpr != vcpu->tpr) {\n+            vcpu->tpr = tpr;\n+            cpu_set_apic_tpr(x86_cpu->apic_state, tpr);\n+        }\n     }\n \n     /* 8 Debug Registers - Skipped */\n@@ -1660,7 +1665,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu)\n \n     /* Sync the TPR to the CR8 if was modified during the intercept */\n     tpr = cpu_get_apic_tpr(x86_cpu->apic_state);\n-    if (tpr != vcpu->tpr) {\n+    if (!whpx_irqchip_in_kernel() && tpr != vcpu->tpr) {\n         vcpu->tpr = tpr;\n         reg_values[reg_count].Reg64 = tpr;\n         qatomic_set(&cpu->exit_request, true);\n@@ -1702,12 +1707,14 @@ static void whpx_vcpu_post_run(CPUState *cpu)\n \n     env->eflags = vcpu->exit_ctx.VpContext.Rflags;\n \n-    uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8;\n-    if (vcpu->tpr != tpr) {\n-        vcpu->tpr = tpr;\n-        bql_lock();\n-        cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n-        bql_unlock();\n+    if (!whpx_irqchip_in_kernel()) {\n+        uint64_t tpr = vcpu->exit_ctx.VpContext.Cr8;\n+        if (vcpu->tpr != tpr) {\n+            vcpu->tpr = tpr;\n+            bql_lock();\n+            cpu_set_apic_tpr(x86_cpu->apic_state, vcpu->tpr);\n+            bql_unlock();\n+        }\n     }\n \n     vcpu->interruption_pending =\n",
    "prefixes": [
        "v9",
        "09/13"
    ]
}