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GET /api/1.1/patches/2220640/?format=api
{ "id": 2220640, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220640/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260407184805.807328-5-dev-josejavier.rodriguez@duagon.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260407184805.807328-5-dev-josejavier.rodriguez@duagon.com>", "date": "2026-04-07T18:48:04", "name": "[RFC,4/5] gpio: mmio: convert accessors to generic register descriptors", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d22e376e885febc7bb3667d6e7450ab28444da34", "submitter": { "id": 92011, "url": "http://patchwork.ozlabs.org/api/1.1/people/92011/?format=api", "name": "Jose Javier Rodriguez Barbarin", "email": "dev-josejavier.rodriguez@duagon.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260407184805.807328-5-dev-josejavier.rodriguez@duagon.com/mbox/", "series": [ { "id": 499020, "url": "http://patchwork.ozlabs.org/api/1.1/series/499020/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=499020", "date": "2026-04-07T18:48:01", "name": "gpio: add PMIO support to gpio-mmio", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499020/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220640/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220640/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-34841-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ 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"0010cf92ddc147dab155d3cfc9f2197e", "From": "Jose Javier Rodriguez Barbarin <dev-josejavier.rodriguez@duagon.com>", "To": "linusw@kernel.org,\n\tbrgl@kernel.org", "Cc": "linux-gpio@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tJose Javier Rodriguez Barbarin <dev-josejavier.rodriguez@duagon.com>", "Subject": "[RFC PATCH 4/5] gpio: mmio: convert accessors to generic register\n descriptors", "Date": "Tue, 7 Apr 2026 20:48:04 +0200", "Message-ID": "<20260407184805.807328-5-dev-josejavier.rodriguez@duagon.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260407184805.807328-1-dev-josejavier.rodriguez@duagon.com>", "References": "<20260407184805.807328-1-dev-josejavier.rodriguez@duagon.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "MA3P292CA0072.ESPP292.PROD.OUTLOOK.COM\n (2603:10a6:250:49::17) To ZR0P278MB0523.CHEP278.PROD.OUTLOOK.COM\n (2603:10a6:910:34::6)", "Precedence": "bulk", "X-Mailing-List": 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"X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Apr 2026 18:49:23.7902\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e50c837f-201f-4046-ce72-08de94d66307", "X-MS-Exchange-CrossTenant-Id": "e5e7e96e-8a28-45d6-9093-a40dd5b51a57", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=e5e7e96e-8a28-45d6-9093-a40dd5b51a57;Ip=[2a01:4f8:a0:13df::219];Helo=[hz-deliver01.de.seppmail.cloud]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tAM4PEPF00027A65.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem" }, "content": "Convert the gpio-mmio accessors to use struct gpio_chip_reg instead of\nthe previous MMIO-only register type.\n\nThis allows the same accessors to operate on both MMIO and PMIO\nregisters and aligns gpio-mmio with the updated gpio_generic_chip API.\n\nSigned-off-by: Jose Javier Rodriguez Barbarin <dev-josejavier.rodriguez@duagon.com>\n---\n drivers/gpio/gpio-mmio.c | 174 ++++++++++++++++++++---------------\n include/linux/gpio/generic.h | 24 +++--\n 2 files changed, 117 insertions(+), 81 deletions(-)", "diff": "diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c\nindex 37e1ed6569e6..247ce5b76441 100644\n--- a/drivers/gpio/gpio-mmio.c\n+++ b/drivers/gpio/gpio-mmio.c\n@@ -62,66 +62,83 @@ o ` ~~~~\\___/~~~~ ` controller in FPGA is ,.`\n \n #include \"gpiolib.h\"\n \n-static void gpio_mmio_write8(void __iomem *reg, unsigned long data)\n+static void gpio_mmio_write8(struct gpio_chip_reg *reg, unsigned long data)\n {\n-\twriteb(data, reg);\n+\twriteb(data, reg->mmio);\n }\n \n-static unsigned long gpio_mmio_read8(void __iomem *reg)\n+static unsigned long gpio_mmio_read8(struct gpio_chip_reg *reg)\n {\n-\treturn readb(reg);\n+\treturn readb(reg->mmio);\n }\n \n-static void gpio_mmio_write16(void __iomem *reg, unsigned long data)\n+static void gpio_mmio_write16(struct gpio_chip_reg *reg, unsigned long data)\n {\n-\twritew(data, reg);\n+\twritew(data, reg->mmio);\n }\n \n-static unsigned long gpio_mmio_read16(void __iomem *reg)\n+static unsigned long gpio_mmio_read16(struct gpio_chip_reg *reg)\n {\n-\treturn readw(reg);\n+\treturn readw(reg->mmio);\n }\n \n-static void gpio_mmio_write32(void __iomem *reg, unsigned long data)\n+static void gpio_mmio_write32(struct gpio_chip_reg *reg, unsigned long data)\n {\n-\twritel(data, reg);\n+\twritel(data, reg->mmio);\n }\n \n-static unsigned long gpio_mmio_read32(void __iomem *reg)\n+static unsigned long gpio_mmio_read32(struct gpio_chip_reg *reg)\n {\n-\treturn readl(reg);\n+\treturn readl(reg->mmio);\n }\n \n #if BITS_PER_LONG >= 64\n-static void gpio_mmio_write64(void __iomem *reg, unsigned long data)\n+static void gpio_mmio_write64(struct gpio_chip_reg *reg, unsigned long data)\n {\n-\twriteq(data, reg);\n+\twriteq(data, reg->mmio);\n }\n \n-static unsigned long gpio_mmio_read64(void __iomem *reg)\n+static unsigned long gpio_mmio_read64(struct gpio_chip_reg *reg)\n {\n-\treturn readq(reg);\n+\treturn readq(reg->mmio);\n }\n #endif /* BITS_PER_LONG >= 64 */\n \n-static void gpio_mmio_write16be(void __iomem *reg, unsigned long data)\n+static void gpio_mmio_write16be(struct gpio_chip_reg *reg, unsigned long data)\n {\n-\tiowrite16be(data, reg);\n+\tiowrite16be(data, reg->mmio);\n }\n \n-static unsigned long gpio_mmio_read16be(void __iomem *reg)\n+static unsigned long gpio_mmio_read16be(struct gpio_chip_reg *reg)\n {\n-\treturn ioread16be(reg);\n+\treturn ioread16be(reg->mmio);\n }\n \n-static void gpio_mmio_write32be(void __iomem *reg, unsigned long data)\n+static void gpio_mmio_write32be(struct gpio_chip_reg *reg, unsigned long data)\n {\n-\tiowrite32be(data, reg);\n+\tiowrite32be(data, reg->mmio);\n }\n \n-static unsigned long gpio_mmio_read32be(void __iomem *reg)\n+static unsigned long gpio_mmio_read32be(struct gpio_chip_reg *reg)\n {\n-\treturn ioread32be(reg);\n+\treturn ioread32be(reg->mmio);\n+}\n+\n+static inline void gpio_chip_reg_init(struct gpio_chip_reg *reg, bool io_port,\n+\t\t\t\t void __iomem *addr, unsigned long port)\n+{\n+\treg->mmio = NULL;\n+\treg->port = 0;\n+\n+\tif (io_port)\n+\t\treg->port = port;\n+\telse\n+\t\treg->mmio = addr;\n+}\n+\n+static inline bool gpio_chip_reg_is_set(struct gpio_chip_reg *reg)\n+{\n+\treturn reg->mmio != NULL || reg->port != 0;\n }\n \n static unsigned long gpio_mmio_line2mask(struct gpio_chip *gc, unsigned int line)\n@@ -140,9 +157,9 @@ static int gpio_mmio_get_set(struct gpio_chip *gc, unsigned int gpio)\n \tbool dir = !!(chip->sdir & pinmask);\n \n \tif (dir)\n-\t\treturn !!(chip->read_reg(chip->reg_set) & pinmask);\n+\t\treturn !!(chip->read_reg(&chip->reg_set) & pinmask);\n \n-\treturn !!(chip->read_reg(chip->reg_dat) & pinmask);\n+\treturn !!(chip->read_reg(&chip->reg_dat) & pinmask);\n }\n \n /*\n@@ -162,9 +179,9 @@ static int gpio_mmio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,\n \tget_mask = *mask & ~chip->sdir;\n \n \tif (set_mask)\n-\t\t*bits |= chip->read_reg(chip->reg_set) & set_mask;\n+\t\t*bits |= chip->read_reg(&chip->reg_set) & set_mask;\n \tif (get_mask)\n-\t\t*bits |= chip->read_reg(chip->reg_dat) & get_mask;\n+\t\t*bits |= chip->read_reg(&chip->reg_dat) & get_mask;\n \n \treturn 0;\n }\n@@ -173,7 +190,7 @@ static int gpio_mmio_get(struct gpio_chip *gc, unsigned int gpio)\n {\n \tstruct gpio_generic_chip *chip = to_gpio_generic_chip(gc);\n \n-\treturn !!(chip->read_reg(chip->reg_dat) & gpio_mmio_line2mask(gc, gpio));\n+\treturn !!(chip->read_reg(&chip->reg_dat) & gpio_mmio_line2mask(gc, gpio));\n }\n \n /*\n@@ -186,7 +203,7 @@ static int gpio_mmio_get_multiple(struct gpio_chip *gc, unsigned long *mask,\n \n \t/* Make sure we first clear any bits that are zero when we read the register */\n \t*bits &= ~*mask;\n-\t*bits |= chip->read_reg(chip->reg_dat) & *mask;\n+\t*bits |= chip->read_reg(&chip->reg_dat) & *mask;\n \treturn 0;\n }\n \n@@ -209,7 +226,7 @@ static int gpio_mmio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,\n \t\treadmask |= gpio_mmio_line2mask(gc, bit);\n \n \t/* Read the register */\n-\tval = chip->read_reg(chip->reg_dat) & readmask;\n+\tval = chip->read_reg(&chip->reg_dat) & readmask;\n \n \t/*\n \t * Mirror the result into the \"bits\" result, this will give line 0\n@@ -238,7 +255,7 @@ static int gpio_mmio_set(struct gpio_chip *gc, unsigned int gpio, int val)\n \telse\n \t\tchip->sdata &= ~mask;\n \n-\tchip->write_reg(chip->reg_dat, chip->sdata);\n+\tchip->write_reg(&chip->reg_dat, chip->sdata);\n \n \treturn 0;\n }\n@@ -250,9 +267,9 @@ static int gpio_mmio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,\n \tunsigned long mask = gpio_mmio_line2mask(gc, gpio);\n \n \tif (val)\n-\t\tchip->write_reg(chip->reg_set, mask);\n+\t\tchip->write_reg(&chip->reg_set, mask);\n \telse\n-\t\tchip->write_reg(chip->reg_clr, mask);\n+\t\tchip->write_reg(&chip->reg_clr, mask);\n \n \treturn 0;\n }\n@@ -269,7 +286,7 @@ static int gpio_mmio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)\n \telse\n \t\tchip->sdata &= ~mask;\n \n-\tchip->write_reg(chip->reg_set, chip->sdata);\n+\tchip->write_reg(&chip->reg_set, chip->sdata);\n \n \treturn 0;\n }\n@@ -297,7 +314,7 @@ static void gpio_mmio_multiple_get_masks(struct gpio_chip *gc,\n static void gpio_mmio_set_multiple_single_reg(struct gpio_chip *gc,\n \t\t\t\t\t unsigned long *mask,\n \t\t\t\t\t unsigned long *bits,\n-\t\t\t\t\t void __iomem *reg)\n+\t\t\t\t\t struct gpio_chip_reg *reg)\n {\n \tstruct gpio_generic_chip *chip = to_gpio_generic_chip(gc);\n \tunsigned long set_mask, clear_mask;\n@@ -317,7 +334,7 @@ static int gpio_mmio_set_multiple(struct gpio_chip *gc, unsigned long *mask,\n {\n \tstruct gpio_generic_chip *chip = to_gpio_generic_chip(gc);\n \n-\tgpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_dat);\n+\tgpio_mmio_set_multiple_single_reg(gc, mask, bits, &chip->reg_dat);\n \n \treturn 0;\n }\n@@ -327,7 +344,7 @@ static int gpio_mmio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,\n {\n \tstruct gpio_generic_chip *chip = to_gpio_generic_chip(gc);\n \n-\tgpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_set);\n+\tgpio_mmio_set_multiple_single_reg(gc, mask, bits, &chip->reg_set);\n \n \treturn 0;\n }\n@@ -342,9 +359,9 @@ static int gpio_mmio_set_multiple_with_clear(struct gpio_chip *gc,\n \tgpio_mmio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);\n \n \tif (set_mask)\n-\t\tchip->write_reg(chip->reg_set, set_mask);\n+\t\tchip->write_reg(&chip->reg_set, set_mask);\n \tif (clear_mask)\n-\t\tchip->write_reg(chip->reg_clr, clear_mask);\n+\t\tchip->write_reg(&chip->reg_clr, clear_mask);\n \n \treturn 0;\n }\n@@ -394,10 +411,10 @@ static int gpio_mmio_dir_in(struct gpio_chip *gc, unsigned int gpio)\n \tscoped_guard(raw_spinlock_irqsave, &chip->lock) {\n \t\tchip->sdir &= ~gpio_mmio_line2mask(gc, gpio);\n \n-\t\tif (chip->reg_dir_in)\n-\t\t\tchip->write_reg(chip->reg_dir_in, ~chip->sdir);\n-\t\tif (chip->reg_dir_out)\n-\t\t\tchip->write_reg(chip->reg_dir_out, chip->sdir);\n+\t\tif (gpio_chip_reg_is_set(&chip->reg_dir_in))\n+\t\t\tchip->write_reg(&chip->reg_dir_in, ~chip->sdir);\n+\t\tif (gpio_chip_reg_is_set(&chip->reg_dir_out))\n+\t\t\tchip->write_reg(&chip->reg_dir_out, chip->sdir);\n \t}\n \n \treturn gpio_mmio_dir_return(gc, gpio, false);\n@@ -414,14 +431,14 @@ static int gpio_mmio_get_dir(struct gpio_chip *gc, unsigned int gpio)\n \t\treturn GPIO_LINE_DIRECTION_IN;\n \t}\n \n-\tif (chip->reg_dir_out) {\n-\t\tif (chip->read_reg(chip->reg_dir_out) & gpio_mmio_line2mask(gc, gpio))\n+\tif (gpio_chip_reg_is_set(&chip->reg_dir_out)) {\n+\t\tif (chip->read_reg(&chip->reg_dir_out) & gpio_mmio_line2mask(gc, gpio))\n \t\t\treturn GPIO_LINE_DIRECTION_OUT;\n \t\treturn GPIO_LINE_DIRECTION_IN;\n \t}\n \n-\tif (chip->reg_dir_in)\n-\t\tif (!(chip->read_reg(chip->reg_dir_in) & gpio_mmio_line2mask(gc, gpio)))\n+\tif (gpio_chip_reg_is_set(&chip->reg_dir_in))\n+\t\tif (!(chip->read_reg(&chip->reg_dir_in) & gpio_mmio_line2mask(gc, gpio)))\n \t\t\treturn GPIO_LINE_DIRECTION_OUT;\n \n \treturn GPIO_LINE_DIRECTION_IN;\n@@ -435,10 +452,10 @@ static void gpio_mmio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)\n \n \tchip->sdir |= gpio_mmio_line2mask(gc, gpio);\n \n-\tif (chip->reg_dir_in)\n-\t\tchip->write_reg(chip->reg_dir_in, ~chip->sdir);\n-\tif (chip->reg_dir_out)\n-\t\tchip->write_reg(chip->reg_dir_out, chip->sdir);\n+\tif (gpio_chip_reg_is_set(&chip->reg_dir_in))\n+\t\tchip->write_reg(&chip->reg_dir_in, ~chip->sdir);\n+\tif (gpio_chip_reg_is_set(&chip->reg_dir_out))\n+\t\tchip->write_reg(&chip->reg_dir_out, chip->sdir);\n }\n \n static int gpio_mmio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio,\n@@ -504,6 +521,20 @@ static int gpio_mmio_setup_accessors(struct device *dev,\n \treturn 0;\n }\n \n+/*\n+ * Initialize registers based on whether the config is io_port or not.\n+ */\n+static void gpio_mmio_setup_regs(struct gpio_generic_chip *chip,\n+\t\t\t const struct gpio_generic_chip_config *cfg)\n+{\n+\tgpio_chip_reg_init(&chip->reg_dat, chip->io_port, cfg->dat, cfg->dat_port);\n+\tgpio_chip_reg_init(&chip->reg_dat, chip->io_port, cfg->dat, cfg->dat_port);\n+\tgpio_chip_reg_init(&chip->reg_set, chip->io_port, cfg->set, cfg->set_port);\n+\tgpio_chip_reg_init(&chip->reg_clr, chip->io_port, cfg->clr, cfg->clr_port);\n+\tgpio_chip_reg_init(&chip->reg_dir_in, chip->io_port, cfg->dirin, cfg->dirin_port);\n+\tgpio_chip_reg_init(&chip->reg_dir_out, chip->io_port, cfg->dirout, cfg->dirout_port);\n+}\n+\n /*\n * Create the device and allocate the resources. For setting GPIO's there are\n * three supported configurations:\n@@ -531,17 +562,15 @@ static int gpio_mmio_setup_io(struct gpio_generic_chip *chip,\n {\n \tstruct gpio_chip *gc = &chip->gc;\n \n-\tchip->reg_dat = cfg->dat;\n-\tif (!chip->reg_dat)\n+\tif (!gpio_chip_reg_is_set(&chip->reg_dat))\n \t\treturn -EINVAL;\n \n-\tif (cfg->set && cfg->clr) {\n-\t\tchip->reg_set = cfg->set;\n-\t\tchip->reg_clr = cfg->clr;\n+\tif (gpio_chip_reg_is_set(&chip->reg_set) &&\n+\t gpio_chip_reg_is_set(&chip->reg_clr)) {\n \t\tgc->set = gpio_mmio_set_with_clear;\n \t\tgc->set_multiple = gpio_mmio_set_multiple_with_clear;\n-\t} else if (cfg->set && !cfg->clr) {\n-\t\tchip->reg_set = cfg->set;\n+\t} else if (gpio_chip_reg_is_set(&chip->reg_set) &&\n+\t\t !gpio_chip_reg_is_set(&chip->reg_clr)) {\n \t\tgc->set = gpio_mmio_set_set;\n \t\tgc->set_multiple = gpio_mmio_set_multiple_set;\n \t} else if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) {\n@@ -579,10 +608,8 @@ static int gpio_mmio_setup_direction(struct gpio_generic_chip *chip,\n \t\t\t\t const struct gpio_generic_chip_config *cfg)\n {\n \tstruct gpio_chip *gc = &chip->gc;\n-\n-\tif (cfg->dirout || cfg->dirin) {\n-\t\tchip->reg_dir_out = cfg->dirout;\n-\t\tchip->reg_dir_in = cfg->dirin;\n+\tif (gpio_chip_reg_is_set(&chip->reg_dir_out) ||\n+\tgpio_chip_reg_is_set(&chip->reg_dir_in)) {\n \t\tif (cfg->flags & GPIO_GENERIC_NO_SET_ON_INPUT)\n \t\t\tgc->direction_output = gpio_mmio_dir_out_dir_first;\n \t\telse\n@@ -651,6 +678,8 @@ int gpio_generic_chip_init(struct gpio_generic_chip *chip,\n \tif (ret)\n \t\tgc->ngpio = chip->bits;\n \n+\tgpio_mmio_setup_regs(chip, cfg);\n+\n \tret = gpio_mmio_setup_io(chip, cfg);\n \tif (ret)\n \t\treturn ret;\n@@ -670,10 +699,10 @@ int gpio_generic_chip_init(struct gpio_generic_chip *chip,\n \t\tgc->free = gpiochip_generic_free;\n \t}\n \n-\tchip->sdata = chip->read_reg(chip->reg_dat);\n+\tchip->sdata = chip->read_reg(&chip->reg_dat);\n \tif (gc->set == gpio_mmio_set_set &&\n \t\t\t!(flags & GPIO_GENERIC_UNREADABLE_REG_SET))\n-\t\tchip->sdata = chip->read_reg(chip->reg_set);\n+\t\tchip->sdata = chip->read_reg(&chip->reg_set);\n \n \tif (flags & GPIO_GENERIC_UNREADABLE_REG_DIR)\n \t\tchip->dir_unreadable = true;\n@@ -681,20 +710,21 @@ int gpio_generic_chip_init(struct gpio_generic_chip *chip,\n \t/*\n \t * Inspect hardware to find initial direction setting.\n \t */\n-\tif ((chip->reg_dir_out || chip->reg_dir_in) &&\n+\tif ((gpio_chip_reg_is_set(&chip->reg_dir_out) || gpio_chip_reg_is_set(&chip->reg_dir_in)) &&\n \t !(flags & GPIO_GENERIC_UNREADABLE_REG_DIR)) {\n-\t\tif (chip->reg_dir_out)\n-\t\t\tchip->sdir = chip->read_reg(chip->reg_dir_out);\n-\t\telse if (chip->reg_dir_in)\n-\t\t\tchip->sdir = ~chip->read_reg(chip->reg_dir_in);\n+\t\tif (gpio_chip_reg_is_set(&chip->reg_dir_out))\n+\t\t\tchip->sdir = chip->read_reg(&chip->reg_dir_out);\n+\t\telse if (gpio_chip_reg_is_set(&chip->reg_dir_in))\n+\t\t\tchip->sdir = ~chip->read_reg(&chip->reg_dir_in);\n \t\t/*\n \t\t * If we have two direction registers, synchronise\n \t\t * input setting to output setting, the library\n \t\t * can not handle a line being input and output at\n \t\t * the same time.\n \t\t */\n-\t\tif (chip->reg_dir_out && chip->reg_dir_in)\n-\t\t\tchip->write_reg(chip->reg_dir_in, ~chip->sdir);\n+\t\tif (gpio_chip_reg_is_set(&chip->reg_dir_out) &&\n+\t\t gpio_chip_reg_is_set(&chip->reg_dir_in))\n+\t\t\tchip->write_reg(&chip->reg_dir_in, ~chip->sdir);\n \t}\n \n \treturn ret;\ndiff --git a/include/linux/gpio/generic.h b/include/linux/gpio/generic.h\nindex eec63f8fe144..d0de8f77d0bc 100644\n--- a/include/linux/gpio/generic.h\n+++ b/include/linux/gpio/generic.h\n@@ -108,15 +108,15 @@ struct gpio_chip_reg {\n */\n struct gpio_generic_chip {\n \tstruct gpio_chip gc;\n-\tunsigned long (*read_reg)(void __iomem *reg);\n-\tvoid (*write_reg)(void __iomem *reg, unsigned long data);\n+\tunsigned long (*read_reg)(struct gpio_chip_reg *reg);\n+\tvoid (*write_reg)(struct gpio_chip_reg *reg, unsigned long data);\n \tbool be_bits;\n \tbool io_port;\n-\tvoid __iomem *reg_dat;\n-\tvoid __iomem *reg_set;\n-\tvoid __iomem *reg_clr;\n-\tvoid __iomem *reg_dir_out;\n-\tvoid __iomem *reg_dir_in;\n+\tstruct gpio_chip_reg reg_dat;\n+\tstruct gpio_chip_reg reg_set;\n+\tstruct gpio_chip_reg reg_clr;\n+\tstruct gpio_chip_reg reg_dir_out;\n+\tstruct gpio_chip_reg reg_dir_in;\n \tbool dir_unreadable;\n \tbool pinctrl;\n \tint bits;\n@@ -168,10 +168,13 @@ gpio_generic_chip_set(struct gpio_generic_chip *chip, unsigned int offset,\n static inline unsigned long\n gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg)\n {\n+\tstruct gpio_chip_reg rg;\n+\n \tif (WARN_ON(!chip->read_reg))\n \t\treturn 0;\n \n-\treturn chip->read_reg(reg);\n+\trg.mmio = reg;\n+\treturn chip->read_reg(&rg);\n }\n \n /**\n@@ -183,10 +186,13 @@ gpio_generic_read_reg(struct gpio_generic_chip *chip, void __iomem *reg)\n static inline void gpio_generic_write_reg(struct gpio_generic_chip *chip,\n \t\t\t\t\t void __iomem *reg, unsigned long val)\n {\n+\tstruct gpio_chip_reg rg;\n+\n \tif (WARN_ON(!chip->write_reg))\n \t\treturn;\n \n-\tchip->write_reg(reg, val);\n+\trg.mmio = reg;\n+\tchip->write_reg(&rg, val);\n }\n \n #define gpio_generic_chip_lock(gen_gc) \\\n", "prefixes": [ "RFC", "4/5" ] }