Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2220533/?format=api
{ "id": 2220533, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220533/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260407130450.1489318-4-18255117159@163.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260407130450.1489318-4-18255117159@163.com>", "date": "2026-04-07T13:04:50", "name": "[v7,3/3] PCI: dwc: Use common speed conversion function", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "274475b73b6eb9a5b0f02418f53f959e07e9ab6a", "submitter": { "id": 89937, "url": "http://patchwork.ozlabs.org/api/1.1/people/89937/?format=api", "name": "Hans Zhang", "email": "18255117159@163.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260407130450.1489318-4-18255117159@163.com/mbox/", "series": [ { "id": 498981, "url": "http://patchwork.ozlabs.org/api/1.1/series/498981/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498981", "date": "2026-04-07T13:04:48", "name": "PCI: Refactor PCIe speed validation and conversion functions", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/498981/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220533/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220533/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-52066-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=J8qg2oMI;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52066-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=\"J8qg2oMI\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=117.135.210.2", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=163.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fqmhS39Hyz1yGf\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 07 Apr 2026 23:07:52 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id C8036304A88F\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 7 Apr 2026 13:05:49 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id A850E372B3B;\n\tTue, 7 Apr 2026 13:05:48 +0000 (UTC)", "from m16.mail.163.com (m16.mail.163.com [117.135.210.2])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id E222614F70;\n\tTue, 7 Apr 2026 13:05:42 +0000 (UTC)", "from Precision-7960.. (unknown [])\n\tby gzga-smtp-mtada-g1-1 (Coremail) with SMTP id\n _____wC33bQHAdVpBqSeDg--.5276S5;\n\tTue, 07 Apr 2026 21:05:15 +0800 (CST)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775567148; cv=none;\n b=mSN7CKzF9q4wXS+pCGYMKZDJbI2SzWny6UddQ/0G9FNkupFvXOPLlnGOg0F4tkh6yoyoTKv5GMsLE7oR/1ENx9NlgkZYWbRi93BjEkM59sb/dcxoz7cvwOJSDgbXFj8fHAj6hxoFbFJDuUdAVcJQaEULlfVcbpWNgj92n9SUuQg=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775567148; c=relaxed/simple;\n\tbh=SRuCRSGlXlqfZsBEu0MZCS+EvTNV5OpFHGi/uezedFI=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=DvGJkKbL0E+2XIdsY8hUWItmhAonD0+gbs43dn9wTUsYwmX5b9kqhsElOcbnT/nHcQ/9Qzrp4jbhKeQdF6Bn9vPwtGKnhFVqgOlDB7G81VXuRKGXZvEnqZK9MFnhAQpqKgMWf4c0fEuqNJZ1wRvDc+qcm5gGwiA7UZRqzWr+Se8=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=163.com;\n spf=pass smtp.mailfrom=163.com;\n dkim=pass (1024-bit key) header.d=163.com header.i=@163.com\n header.b=J8qg2oMI; arc=none smtp.client-ip=117.135.210.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n\ts=s110527; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=Cq\n\t9vm1l2WI4hUexxxuph9y/77fqWdij3F2uI4NyEkSg=; b=J8qg2oMIMKxkV1LMEM\n\tCWmGvpzVqKbILokEPY4lEFFRUIBEkqlmnCUCOPHFRZYaLRB2nmEDUfXcL25pq2wm\n\tMS9szAbZgB/8x/E5ivDugrd1BdWmGa3aFlrkEfR7lQRVT6gpBPP02dkXPFMBWR71\n\tTS6Ws4+ik7rJLWgEM5y/oytlA=", "From": "Hans Zhang <18255117159@163.com>", "To": "bhelgaas@google.com,\n\tlpieralisi@kernel.org,\n\tkw@linux.com,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tilpo.jarvinen@linux.intel.com,\n\tjingoohan1@gmail.com", "Cc": "robh@kernel.org,\n\tlinux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tHans Zhang <18255117159@163.com>,\n\tShawn Lin <shawn.lin@rock-chips.com>", "Subject": "[PATCH v7 3/3] PCI: dwc: Use common speed conversion function", "Date": "Tue, 7 Apr 2026 21:04:50 +0800", "Message-Id": "<20260407130450.1489318-4-18255117159@163.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260407130450.1489318-1-18255117159@163.com>", "References": "<20260407130450.1489318-1-18255117159@163.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "_____wC33bQHAdVpBqSeDg--.5276S5", "X-Coremail-Antispam": "1Uf129KBjvJXoWxAw1UCr1xWr13GF43uryxuFg_yoW5Gr1Upa\n\t9xZr40vF48Jr43urs09as5Xa4UXFnxCr4DCFZ8W3sYvFy2yasxWa10y34ft34akrZ2yr1a\n\t9w17JrW5C3W7tF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n\t9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x0zR5UUUUUUUU=", "X-CM-SenderInfo": "rpryjkyvrrlimvzbiqqrwthudrp/xtbC6wwTtmnVAQyqLgAA33" }, "content": "Replace the private switch-based speed conversion in\ndw_pcie_link_set_max_speed() with the public pci_bus_speed2lnkctl2()\nfunction.\n\nThis eliminates duplicate conversion logic and ensures consistency with\nother PCIe drivers, while handling invalid speeds by falling back to\nhardware capabilities.\n\nSigned-off-by: Hans Zhang <18255117159@163.com>\nReviewed-by: Shawn Lin <shawn.lin@rock-chips.com>\nAcked-by: Manivannan Sadhasivam <mani@kernel.org>\n---\n drivers/pci/controller/dwc/pcie-designware.c | 28 +++++++-------------\n 1 file changed, 9 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c\nindex 06792ba92aa7..10895f6a8e6e 100644\n--- a/drivers/pci/controller/dwc/pcie-designware.c\n+++ b/drivers/pci/controller/dwc/pcie-designware.c\n@@ -843,8 +843,10 @@ EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup);\n \n static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)\n {\n-\tu32 cap, ctrl2, link_speed;\n+\tu32 cap, ctrl2;\n+\tenum pci_bus_speed link_speed;\n \tu8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);\n+\tu16 ctrl2_speed;\n \n \tcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);\n \n@@ -861,30 +863,18 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)\n \tctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);\n \tctrl2 &= ~PCI_EXP_LNKCTL2_TLS;\n \n-\tswitch (pcie_get_link_speed(pci->max_link_speed)) {\n-\tcase PCIE_SPEED_2_5GT:\n-\t\tlink_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;\n-\t\tbreak;\n-\tcase PCIE_SPEED_5_0GT:\n-\t\tlink_speed = PCI_EXP_LNKCTL2_TLS_5_0GT;\n-\t\tbreak;\n-\tcase PCIE_SPEED_8_0GT:\n-\t\tlink_speed = PCI_EXP_LNKCTL2_TLS_8_0GT;\n-\t\tbreak;\n-\tcase PCIE_SPEED_16_0GT:\n-\t\tlink_speed = PCI_EXP_LNKCTL2_TLS_16_0GT;\n-\t\tbreak;\n-\tdefault:\n+\tlink_speed = pcie_get_link_speed(pci->max_link_speed);\n+\tctrl2_speed = pci_bus_speed2lnkctl2(link_speed);\n+\tif (ctrl2_speed == 0) {\n \t\t/* Use hardware capability */\n-\t\tlink_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);\n+\t\tctrl2_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);\n \t\tctrl2 &= ~PCI_EXP_LNKCTL2_HASD;\n-\t\tbreak;\n \t}\n \n-\tdw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed);\n+\tdw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | ctrl2_speed);\n \n \tcap &= ~((u32)PCI_EXP_LNKCAP_SLS);\n-\tdw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed);\n+\tdw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | ctrl2_speed);\n \n }\n \n", "prefixes": [ "v7", "3/3" ] }