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GET /api/1.1/patches/2220525/?format=api
{ "id": 2220525, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220525/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260407-d3cold-v4-5-bb171f75b465@oss.qualcomm.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260407-d3cold-v4-5-bb171f75b465@oss.qualcomm.com>", "date": "2026-04-07T13:03:12", "name": "[v4,5/5] PCI: qcom: Add D3cold support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7b5caabbf33cc627b0bf251e1aad30b626a4ca6e", "submitter": { "id": 89908, "url": "http://patchwork.ozlabs.org/api/1.1/people/89908/?format=api", "name": "Krishna Chaitanya Chundru", "email": "krishna.chundru@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260407-d3cold-v4-5-bb171f75b465@oss.qualcomm.com/mbox/", "series": [ { "id": 498980, "url": "http://patchwork.ozlabs.org/api/1.1/series/498980/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498980", "date": "2026-04-07T13:03:07", "name": "PCI: qcom: Add D3cold support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/498980/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220525/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220525/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-52064-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=bCnvo+02;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=SBPvjqDH;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260407-d3cold-v4-5-bb171f75b465@oss.qualcomm.com>", "References": "<20260407-d3cold-v4-0-bb171f75b465@oss.qualcomm.com>", "In-Reply-To": "<20260407-d3cold-v4-0-bb171f75b465@oss.qualcomm.com>", "To": "Jingoo Han <jingoohan1@gmail.com>,\n Manivannan Sadhasivam <mani@kernel.org>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Will Deacon <will@kernel.org>", "Cc": "linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775566995; l=7930;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=W1OhNcEspfBwAlfmZve2ZqD5tZvvm1E8mVApzAXXGuI=;\n b=o5n5mzRCb1hInEwIP9Lo/mkqs1V+NaPD+q4D06Qd+qeyiIvLq3qU775agBpWtloe/QTme7jjR\n nCXcRkr1zXNBKMFJTclv0uXBflgy6ODXlnpBwnYuu/TuB08Ps/73MqU", "X-Developer-Key": "i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=", "X-Proofpoint-ORIG-GUID": "wxUSY-AF3roXzLfZDjaMRphm1QC__uUS", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDA3MDEyMSBTYWx0ZWRfXxaCMyLE8NleC\n wAMRXNm+9Mce5N8Y87JTMfZEsjFKb0jt8awPeOfllIjMdIP67HpRzsbVGFSdTn0WhYawM20eKBL\n BbSQV4owTMLo30ILUcru3gBK8z59o1WkVkD25e4mf7DVfMVbdgygdg60P9kebrnu3aIcnOiwk8i\n TO2eP6tY+brOsr8+467Fxt9YP1sUNi2q0FY4ju1ifFW+HHnvsNOWdZ4TE3QFzMfFKhIh1Rc/s+O\n FP9i9xyS8y//03m9wMU17thGml26qRKCdCSIvmRSzljmWg6GZYB5oSrAYV1/9EVgKP87f64lYHu\n QNZEYeb+Ett+WCtbK3O83XxoTDswByDWhsRS5UZVzqB+hihgziFqCljmfNcJoasyuL7UAnAeNgz\n UBz63TeuA/L9xnsyeH5Ze6vxC36MNFkj+So7lNjB1yhc3RQ5WFClyYocqWKRT/qhUect73VevMs\n 3r9JQGiHX64UkcKdH/A==", "X-Proofpoint-GUID": "wxUSY-AF3roXzLfZDjaMRphm1QC__uUS", "X-Authority-Analysis": "v=2.4 cv=D/d37PRj c=1 sm=1 tr=0 ts=69d500b5 cx=c_pps\n a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22\n a=EUspDBNiAAAA:8 a=3yJ-4rlz3SFKGY1FFUMA:9 a=QEXdDO2ut3YA:10\n a=uG9DUKGECoFWVXl0Dc02:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-07_02,2026-04-07_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n suspectscore=0 adultscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0\n priorityscore=1501 malwarescore=0 spamscore=0 phishscore=0 clxscore=1015\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604070121" }, "content": "Add support for transitioning PCIe endpoints under host bridge into\nD3cold by integrating with the DWC core suspend/resume helpers.\n\nImplement PME_TurnOff message generation via ELBI_SYS_CTRL and hook it\ninto the DWC host operations so the controller follows the standard\nPME_TurnOff-based power-down sequence before entering D3cold.\n\nWhen the device is suspended into D3cold, fully tear down interconnect\nbandwidth, OPP votes. If D3cold is not entered, retain existing behavior\nby keeping the required interconnect and OPP votes.\n\nUse dw_pcie::skip_pwrctrl_off to avoid powering off devices during suspend\nto preseve wakeup capability of the devices and also not to power on the\ndevices in the init path.\n\nDrop the qcom_pcie::suspended flag and rely on the existing\ndw_pcie::suspended state, which now drives both the power-management\nflow and the interconnect/OPP handling.\n\nSigned-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>\n---\n drivers/pci/controller/dwc/pcie-qcom.c | 150 ++++++++++++++++++++-------------\n 1 file changed, 92 insertions(+), 58 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c\nindex c14c3eb70f356b6ad8a2ffe48b107327d2babf77..e8d109c44dd270610272906244d1afeec3664f41 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom.c\n@@ -145,6 +145,7 @@\n \n /* ELBI_SYS_CTRL register fields */\n #define ELBI_SYS_CTRL_LT_ENABLE\t\t\tBIT(0)\n+#define ELBI_SYS_CTRL_PME_TURNOFF_MSG\t\tBIT(4)\n \n /* AXI_MSTR_RESP_COMP_CTRL0 register fields */\n #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K\t0x4\n@@ -283,7 +284,6 @@ struct qcom_pcie {\n \tconst struct qcom_pcie_cfg *cfg;\n \tstruct dentry *debugfs;\n \tstruct list_head ports;\n-\tbool suspended;\n \tbool use_pm_opp;\n };\n \n@@ -1336,13 +1336,17 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp)\n \tif (ret)\n \t\tgoto err_deinit;\n \n-\tret = pci_pwrctrl_create_devices(pci->dev);\n-\tif (ret)\n-\t\tgoto err_disable_phy;\n+\tif (!pci->suspended) {\n+\t\tret = pci_pwrctrl_create_devices(pci->dev);\n+\t\tif (ret)\n+\t\t\tgoto err_disable_phy;\n+\t}\n \n-\tret = pci_pwrctrl_power_on_devices(pci->dev);\n-\tif (ret)\n-\t\tgoto err_pwrctrl_destroy;\n+\tif (!pp->skip_pwrctrl_off) {\n+\t\tret = pci_pwrctrl_power_on_devices(pci->dev);\n+\t\tif (ret)\n+\t\t\tgoto err_pwrctrl_destroy;\n+\t}\n \n \tif (pcie->cfg->ops->post_init) {\n \t\tret = pcie->cfg->ops->post_init(pcie);\n@@ -1386,11 +1390,14 @@ static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp)\n \n \tqcom_pcie_perst_assert(pcie);\n \n-\t/*\n-\t * No need to destroy pwrctrl devices as this function only gets called\n-\t * during system suspend as of now.\n-\t */\n-\tpci_pwrctrl_power_off_devices(pci->dev);\n+\tif (!pci->pp.skip_pwrctrl_off) {\n+\t\t/*\n+\t\t * No need to destroy pwrctrl devices as this function only gets called\n+\t\t * during system suspend as of now.\n+\t\t */\n+\t\tpci_pwrctrl_power_off_devices(pci->dev);\n+\t}\n+\n \tqcom_pcie_phy_power_off(pcie);\n \tpcie->cfg->ops->deinit(pcie);\n }\n@@ -1404,10 +1411,18 @@ static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp)\n \t\tpcie->cfg->ops->host_post_init(pcie);\n }\n \n+static void qcom_pcie_host_pme_turn_off(struct dw_pcie_rp *pp)\n+{\n+\tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n+\n+\twritel(ELBI_SYS_CTRL_PME_TURNOFF_MSG, pci->elbi_base + ELBI_SYS_CTRL);\n+}\n+\n static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {\n \t.init\t\t= qcom_pcie_host_init,\n \t.deinit\t\t= qcom_pcie_host_deinit,\n \t.post_init\t= qcom_pcie_host_post_init,\n+\t.pme_turn_off\t= qcom_pcie_host_pme_turn_off,\n };\n \n /* Qcom IP rev.: 2.1.0\tSynopsys IP rev.: 4.01a */\n@@ -2072,53 +2087,51 @@ static int qcom_pcie_suspend_noirq(struct device *dev)\n \tif (!pcie)\n \t\treturn 0;\n \n-\t/*\n-\t * Set minimum bandwidth required to keep data path functional during\n-\t * suspend.\n-\t */\n-\tif (pcie->icc_mem) {\n-\t\tret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));\n-\t\tif (ret) {\n-\t\t\tdev_err(dev,\n-\t\t\t\t\"Failed to set bandwidth for PCIe-MEM interconnect path: %d\\n\",\n-\t\t\t\tret);\n-\t\t\treturn ret;\n-\t\t}\n-\t}\n+\tret = dw_pcie_suspend_noirq(pcie->pci);\n+\tif (ret)\n+\t\treturn ret;\n \n-\t/*\n-\t * Turn OFF the resources only for controllers without active PCIe\n-\t * devices. For controllers with active devices, the resources are kept\n-\t * ON and the link is expected to be in L0/L1 (sub)states.\n-\t *\n-\t * Turning OFF the resources for controllers with active PCIe devices\n-\t * will trigger access violation during the end of the suspend cycle,\n-\t * as kernel tries to access the PCIe devices config space for masking\n-\t * MSIs.\n-\t *\n-\t * Also, it is not desirable to put the link into L2/L3 state as that\n-\t * implies VDD supply will be removed and the devices may go into\n-\t * powerdown state. This will affect the lifetime of the storage devices\n-\t * like NVMe.\n-\t */\n-\tif (!dw_pcie_link_up(pcie->pci)) {\n-\t\tqcom_pcie_host_deinit(&pcie->pci->pp);\n-\t\tpcie->suspended = true;\n-\t}\n+\tif (pcie->pci->suspended) {\n+\t\tret = icc_disable(pcie->icc_mem);\n+\t\tif (ret)\n+\t\t\tdev_err(dev, \"Failed to disable PCIe-MEM interconnect path: %d\\n\", ret);\n \n-\t/*\n-\t * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM.\n-\t * Because on some platforms, DBI access can happen very late during the\n-\t * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC\n-\t * error.\n-\t */\n-\tif (pm_suspend_target_state != PM_SUSPEND_MEM) {\n \t\tret = icc_disable(pcie->icc_cpu);\n \t\tif (ret)\n \t\t\tdev_err(dev, \"Failed to disable CPU-PCIe interconnect path: %d\\n\", ret);\n \n \t\tif (pcie->use_pm_opp)\n \t\t\tdev_pm_opp_set_opp(pcie->pci->dev, NULL);\n+\t} else {\n+\t\t/*\n+\t\t * Set minimum bandwidth required to keep data path functional during\n+\t\t * suspend.\n+\t\t */\n+\t\tif (pcie->icc_mem) {\n+\t\t\tret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));\n+\t\t\tif (ret) {\n+\t\t\t\tdev_err(dev,\n+\t\t\t\t\t\"Failed to set bandwidth for PCIe-MEM interconnect path: %d\\n\",\n+\t\t\t\t\tret);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/*\n+\t\t * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM.\n+\t\t * Because on some platforms, DBI access can happen very late during the\n+\t\t * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC\n+\t\t * error.\n+\t\t */\n+\t\tif (pm_suspend_target_state != PM_SUSPEND_MEM) {\n+\t\t\tret = icc_disable(pcie->icc_cpu);\n+\t\t\tif (ret)\n+\t\t\t\tdev_err(dev, \"Failed to disable CPU-PCIe interconnect path: %d\\n\",\n+\t\t\t\t\tret);\n+\n+\t\t\tif (pcie->use_pm_opp)\n+\t\t\t\tdev_pm_opp_set_opp(pcie->pci->dev, NULL);\n+\t\t}\n \t}\n \treturn ret;\n }\n@@ -2132,25 +2145,46 @@ static int qcom_pcie_resume_noirq(struct device *dev)\n \tif (!pcie)\n \t\treturn 0;\n \n-\tif (pm_suspend_target_state != PM_SUSPEND_MEM) {\n+\tif (pcie->pci->suspended) {\n \t\tret = icc_enable(pcie->icc_cpu);\n \t\tif (ret) {\n \t\t\tdev_err(dev, \"Failed to enable CPU-PCIe interconnect path: %d\\n\", ret);\n \t\t\treturn ret;\n \t\t}\n-\t}\n \n-\tif (pcie->suspended) {\n-\t\tret = qcom_pcie_host_init(&pcie->pci->pp);\n-\t\tif (ret)\n-\t\t\treturn ret;\n+\t\tret = icc_enable(pcie->icc_mem);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Failed to enable PCIe-MEM interconnect path: %d\\n\", ret);\n+\t\t\tgoto disable_icc_cpu;\n+\t\t}\n \n-\t\tpcie->suspended = false;\n+\t\t/*\n+\t\t * Ignore -ENODEV & -EIO here since it is expected when no endpoint is\n+\t\t * connected to the PCIe link.\n+\t\t */\n+\t\tret = dw_pcie_resume_noirq(pcie->pci);\n+\t\tif (ret && ret != -ENODEV && ret != -EIO)\n+\t\t\tgoto disable_icc_mem;\n+\t} else {\n+\t\tif (pm_suspend_target_state != PM_SUSPEND_MEM) {\n+\t\t\tret = icc_enable(pcie->icc_cpu);\n+\t\t\tif (ret) {\n+\t\t\t\tdev_err(dev, \"Failed to enable CPU-PCIe interconnect path: %d\\n\",\n+\t\t\t\t\tret);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n \t}\n \n \tqcom_pcie_icc_opp_update(pcie);\n \n \treturn 0;\n+disable_icc_mem:\n+\ticc_disable(pcie->icc_mem);\n+disable_icc_cpu:\n+\ticc_disable(pcie->icc_cpu);\n+\n+\treturn ret;\n }\n \n static const struct of_device_id qcom_pcie_match[] = {\n", "prefixes": [ "v4", "5/5" ] }