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GET /api/1.1/patches/2220470/?format=api
{ "id": 2220470, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2220470/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260407104154.2842132-12-sherry.sun@nxp.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260407104154.2842132-12-sherry.sun@nxp.com>", "date": "2026-04-07T10:41:53", "name": "[V11,11/12] arm64: dts: imx8dxl/qm/qxp: Add Root Port node and PERST property", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "abba5f1ba9856206e772e59eeef6d23581b4ea95", "submitter": { "id": 77063, "url": "http://patchwork.ozlabs.org/api/1.1/people/77063/?format=api", "name": "Sherry Sun", "email": "sherry.sun@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260407104154.2842132-12-sherry.sun@nxp.com/mbox/", "series": [ { "id": 498961, "url": "http://patchwork.ozlabs.org/api/1.1/series/498961/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=498961", "date": "2026-04-07T10:41:47", "name": "pci-imx6: Add support for parsing the reset property in new Root Port binding", "version": 11, "mbox": "http://patchwork.ozlabs.org/series/498961/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2220470/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2220470/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-52036-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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"DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=ar1VoCQOfqxRn9JTafCIhUPdpnR3eh4akKNpCkBDLIQ=;\n b=aNlPQ+xZsRqU5SfolUUyEAmBECGy3fxvdQ8ttZyTw036+TjAfddnwMkukwvETAGz11oIWxZc7gawXF7yL+zVF32X9czMvUNvI+q0zkuCUO4mnh6X1OEMGKn69SnDZVF6TbHuSBdulQe+7VeU+OB65D7IGjAA/0DJYF/zYqR66EQHDL2DAAZnaezHCqZDJltd8OHKwRMn9aLFX5wO8CeMN6psy1AeNyiEZahzW2Jm81Q8TOrZuK5YVjstt/IAlmvVMMxmXbcrIrQAVyP2mJ9UlaK0PVtJB9ioIBWf/eUUinLVpyXoIqdNaS7kG0LBhb0clYlV5ul8IjQ25jsHW6KyAQ==", "From": "Sherry Sun <sherry.sun@nxp.com>", "To": "robh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tFrank.Li@nxp.com,\n\ts.hauer@pengutronix.de,\n\tkernel@pengutronix.de,\n\tfestevam@gmail.com,\n\tlpieralisi@kernel.org,\n\tkwilczynski@kernel.org,\n\tmani@kernel.org,\n\tbhelgaas@google.com,\n\thongxing.zhu@nxp.com,\n\tl.stach@pengutronix.de", "Cc": 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FVJq9Y7CNfpF1f86zoPa3gPBLoMQxnfaCTzbhVsYwZIDmdccyLnRkgbCm/CCDlWjcFMAEVf38R9qL9Zq2hM0dXfVhNWGYv/3k/94oh/hTIF9Xqj5WSFLii2FFjEZ0hxEcuMNqc2mJfpmWCeHCGHz9tkH8NBEuej5Hr8XQv5bDmbIODeNihf2rhIit5Q7TbXS2I83u2xsCvfBO+RJ0KzbcrRHoZnxI8ek09h7O+fqXjSbU/nWB6HdFpggCF9oRFDRe0/LGnk/7feD+oD7v9E3X6uxDMzjQ38Giix+/Qr8Bh4/HMc3URAy792H7aJd0qbOiYXc+qzTjb7yx1BnTPmlvT4ECjBucs3UeegXs2N7x1VxGLUs2cLiG4ApG6kdjjhlpeFOmIje4FXCKF2AEl/SMuEv6V+i0Mqtk1HTRiyMNaueuJaDRxIGj8+8DXhiutgTWc119/qGfLMTU2S39xyxFwXIQ03YCUAnIRIdq5fLLmF6JfiBkbJj5s7JJbxxuIPu1/8cq8SoS/mIl2L/4xUKq8cbSRzIy1Jvpddv7cRFO3NKdbbAhSUKDjRNbZHU2B5E33hZTH6MCEUOvqbiJUFnexqBqvXaPxmROYGZ883ocbPamesbMtvuQnNvwga9PmyM2jK8XI9cXc7uhxmtR4qr3Gcb/9i0H6B1RRrB6aZL74hWSfojZa5fK+H2DFK79pKX+xQ7RKuXlSSOUQt5dLzTPetogaKTr46EpUZdfIyvCD3PZJcEaUl9FpTD+pzS8g5bX8EqVz/QokwEwflrhz/I/fvlZEoTxndBSLJfwl39YiCjNNighpbH3vNJ7vH1He0RLTRAl4w1E4GXkgRPKjaYyTodK/Ze5R0n73axMe+egB/+OqGJJXIQQDhpnDchhyDn353Gqn/jShbiTiOafkkFD1StPAw+kg9ltvhs/9BWpZTwEl8c4xrY7hd9wm0Xc94Lj5pN6JJwN3bgxqcZT4/ehfdmaParbQ0zBDnwBqLB8jUnRw9IFKGvQsNr4IdY+FwkKL1YxQnjAvj+Xuik3NXfiIw0B7Qeob1eyJdRygrHakpXeiPMqjIfWtV6yEtB4yGBu0JDNjBRxo6KEN2kY6PQ4txUa77kEaA32tHKMnARL0skrpeOV0acBmRN3dGRarf4Aw2Fdj4jvUhZ/mz0XcHSXgF47l7gKSkR+m3/bWZILvUSRdsmnf8m0314XSvaxKACauYIfkYFSW7nTZiPLldLp6L6EW/ZI9f3vYaBXrZyPvlPL7b93Lnq0EQonOP+LYboRo1VWbF1cVGZinNBhmhvS5Dya1at5HInKfm9FeAYhINFYkFubSnFXy/hnCHkanVtz7fWTP/dyCc97Wl+xEsIZbKxbxq3sa0py92XwiUxwt+Ck34SY1ta7UihC6QWRsN5x1vGx2k3RJ7RVv2ADw76gVuMD1PXpOJ86D90qB4hM2Dy2b3OzaYwUI3AVdm8ycQq6tMGrregPu70noeCJteLkrjlnDip3Lmpm5qFPnN5fSKjTKcSzJVMqtbGOycvMLiwIqA6hK36VwtGAAPGgKfGIB4/jlh58P0qHGdbRKKSkRT1X/evaHOsjZaOOiy4p3e7FiPfbC55SDlcRfPDxoAawh8N6ytCq998QYFWZPYFGSDFBRU+tho0quByIbgMNehslp5iAMHe2GM/vr1FKUdLbWGyASv3yClj+gH2t59IB4UFvVrL3BYWtvU1AlDoRiD2ePazYq4Xk8Z5MTFGJ1CkVQ==", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 24f43e39-cdec-4a28-017d-08de94926b97", "X-MS-Exchange-CrossTenant-AuthSource": "VI0PR04MB12114.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Apr 2026 10:42:52.8664\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n 3BU1mhXRbHBOzRMo5Dn4XjaWRPoYBOLR/35dxmlpvLfP6qqJbWx65eiWzl6Wv7QA3StD2WW24xKgsuvA5XKfCg==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DB9PR04MB8281" }, "content": "Since describing the PCIe PERST# property under Host Bridge node is now\ndeprecated, it is recommended to add it to the Root Port node, so\ncreating the Root Port node and add the reset-gpios property in Root\nPort.\n\nSigned-off-by: Sherry Sun <sherry.sun@nxp.com>\n---\n .../boot/dts/freescale/imx8-ss-hsio.dtsi | 11 ++++++++++\n arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 5 +++++\n arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 10 +++++++++\n .../boot/dts/freescale/imx8qm-ss-hsio.dtsi | 22 +++++++++++++++++++\n arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 5 +++++\n 5 files changed, 53 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi\nindex 469de8b536b5..009990b2e559 100644\n--- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi\n+++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi\n@@ -78,6 +78,17 @@ pcieb: pcie@5f010000 {\n \t\tpower-domains = <&pd IMX_SC_R_PCIE_B>;\n \t\tfsl,max-link-speed = <3>;\n \t\tstatus = \"disabled\";\n+\n+\t\tpcieb_port0: pcie@0 {\n+\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t};\n \t};\n \n \tpcieb_ep: pcie-ep@5f010000 {\ndiff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts\nindex bc62ae5ca812..39108a915f96 100644\n--- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts\n@@ -675,6 +675,7 @@ &pcie0 {\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pcieb>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pcieb>;\n \tvpcie3v3aux-supply = <®_pcieb>;\n@@ -691,6 +692,10 @@ &pcie0_ep {\n \tstatus = \"disabled\";\n };\n \n+&pcieb_port0 {\n+\treset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n+};\n+\n &sai0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_sai0>;\ndiff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts\nindex 011a89d85961..f706c86137c0 100644\n--- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts\n@@ -810,6 +810,7 @@ &pciea {\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pciea>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pciea>;\n \tvpcie3v3aux-supply = <®_pciea>;\n@@ -817,15 +818,24 @@ &pciea {\n \tstatus = \"okay\";\n };\n \n+&pciea_port0 {\n+\treset-gpios = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;\n+};\n+\n &pcieb {\n \tphys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pcieb>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;\n \tstatus = \"disabled\";\n };\n \n+&pcieb_port0 {\n+\treset-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;\n+};\n+\n &qm_pwm_lvds0 {\n \tpinctrl-names = \"default\";\n \tpinctrl-0 = <&pinctrl_pwm_lvds0>;\ndiff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi\nindex f2c94cdb682b..2e4fbfe0ca16 100644\n--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi\n+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi\n@@ -41,6 +41,17 @@ pcie0: pciea: pcie@5f000000 {\n \t\tpower-domains = <&pd IMX_SC_R_PCIE_A>;\n \t\tfsl,max-link-speed = <3>;\n \t\tstatus = \"disabled\";\n+\n+\t\tpciea_port0: pcie@0 {\n+\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t};\n \t};\n \n \tpcie0_ep: pciea_ep: pcie-ep@5f000000 {\n@@ -91,6 +102,17 @@ pcie1: pcieb: pcie@5f010000 {\n \t\tpower-domains = <&pd IMX_SC_R_PCIE_B>;\n \t\tfsl,max-link-speed = <3>;\n \t\tstatus = \"disabled\";\n+\n+\t\tpcieb_port0: pcie@0 {\n+\t\t\tcompatible = \"pciclass,0604\";\n+\t\t\tdevice_type = \"pci\";\n+\t\t\treg = <0x0 0x0 0x0 0x0 0x0>;\n+\t\t\tbus-range = <0x01 0xff>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t};\n \t};\n \n \tsata: sata@5f020000 {\ndiff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts\nindex 623169f7ddb5..489e174df4c4 100644\n--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts\n+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts\n@@ -730,6 +730,7 @@ &pcie0 {\n \tphy-names = \"pcie-phy\";\n \tpinctrl-0 = <&pinctrl_pcieb>;\n \tpinctrl-names = \"default\";\n+\t/* This property is deprecated, use reset-gpios from the Root Port node. */\n \treset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n \tvpcie-supply = <®_pcieb>;\n \tvpcie3v3aux-supply = <®_pcieb>;\n@@ -746,6 +747,10 @@ &pcie0_ep {\n \tstatus = \"disabled\";\n };\n \n+&pcieb_port0 {\n+\treset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;\n+};\n+\n &scu_key {\n \tstatus = \"okay\";\n };\n", "prefixes": [ "V11", "11/12" ] }