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GET /api/1.1/patches/2219699/?format=api
{ "id": 2219699, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2219699/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260403-winbond-ma35d1-v1-3-e2b08c4c5e35@bootlin.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260403-winbond-ma35d1-v1-3-e2b08c4c5e35@bootlin.com>", "date": "2026-04-03T16:17:11", "name": "[3/3] mtd: spinand: winbond: Clarify when to enable the HS bit", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e7e0ccba7471cc44781047e201681c5d64416e2c", "submitter": { "id": 73368, "url": "http://patchwork.ozlabs.org/api/1.1/people/73368/?format=api", "name": "Miquel Raynal", "email": "miquel.raynal@bootlin.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260403-winbond-ma35d1-v1-3-e2b08c4c5e35@bootlin.com/mbox/", "series": [ { "id": 498672, "url": "http://patchwork.ozlabs.org/api/1.1/series/498672/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=498672", "date": "2026-04-03T16:17:08", "name": "mtd: spinand: winbond: Misc fixes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498672/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2219699/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219699/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=sGu9fBQu;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=bootlin.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.b=\"sGu9fBQu\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=bootlin.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=miquel.raynal@bootlin.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fnVJL26ltz1xtJ\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 04 Apr 2026 07:12:34 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 6CE8884159;\n\tFri, 3 Apr 2026 22:12:00 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id C7926840D8; Fri, 3 Apr 2026 18:17:39 +0200 (CEST)", "from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id E1744840B0\n for <u-boot@lists.denx.de>; Fri, 3 Apr 2026 18:17:37 +0200 (CEST)", "from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233])\n by smtpout-02.galae.net (Postfix) with ESMTPS id 96C1A1A312C;\n Fri, 3 Apr 2026 16:17:37 +0000 (UTC)", "from mail.galae.net (mail.galae.net [212.83.136.155])\n by smtpout-01.galae.net (Postfix) with ESMTPS id 6D8AB603C1;\n Fri, 3 Apr 2026 16:17:37 +0000 (UTC)", "from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon)\n with ESMTPSA id 5E7A9104500FA;\n Fri, 3 Apr 2026 18:17:34 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim;\n t=1775233056; h=from:subject:date:message-id:to:cc:mime-version:content-type:\n content-transfer-encoding:in-reply-to:references;\n bh=gQcHQJoz24TyUAw4tN/RD2C66izTzhrqFZzYFIUF/ig=;\n b=sGu9fBQutTS5UTjca4dNmEJJtwIeOqdc+zbPoQKTwLKLjbczjWYXP3qHtBOuHE7Eb8Kf9S\n rY5bPLMJfNeYaeRA3Y9HOsBUDKginf3QhHpH7qN6SD0VEWo8EwguB7tGNUBVIx8PcZ2wfa\n TKRLrKHZ4EBcOcztVAAwIpKw6PDicalybdpo91WY+4xggp9RThLbOwc/O/brLJG8fffYW4\n psESNImynwjPvesShZxnE5ePBjHrFmAYxCagBCwKXF2G0+ADQDpHXbR8tGe8ViDyNpDTZ2\n Edmt+eI3BoTLhlsjt3MYT/x1xi34Kgp+rTVlQktV67nzgrqiT9BdM6ve6kdEjw==", "From": "Miquel Raynal <miquel.raynal@bootlin.com>", "Date": "Fri, 03 Apr 2026 18:17:11 +0200", "Subject": "[PATCH 3/3] mtd: spinand: winbond: Clarify when to enable the HS bit", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260403-winbond-ma35d1-v1-3-e2b08c4c5e35@bootlin.com>", "References": "<20260403-winbond-ma35d1-v1-0-e2b08c4c5e35@bootlin.com>", "In-Reply-To": "<20260403-winbond-ma35d1-v1-0-e2b08c4c5e35@bootlin.com>", "To": "u-boot@lists.denx.de, Frieder Schrempf <frieder.schrempf@kontron.de>", "Cc": "Thomas Petazzoni <thomas.petazzoni@bootlin.com>,\n Tom Rini <trini@konsulko.com>,\n Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>,\n Michael Trimarchi <michael@amarulasolutions.com>,\n Andrew Goodbody <andrew.goodbody@linaro.org>,\n Quentin Schulz <quentin.schulz@cherry.de>,\n Dario Binacchi <dario.binacchi@amarulasolutions.com>,\n Christian Marangi <ansuelsmth@gmail.com>, Steam Lin <stlin2@winbond.com>,\n Miquel Raynal <miquel.raynal@bootlin.com>", "X-Mailer": "b4 0.14.3", "X-Last-TLS-Session-Version": "TLSv1.3", "X-Mailman-Approved-At": "Fri, 03 Apr 2026 22:11:58 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Above 104MHz when in fast dual or quad I/O reads, the delay between\naddress and data cycles is too short. It is possible to reach higher\nfrequencies, up to 166MHz, by adding a few more dummy cycles through the\nsetting of the HS bit. Improve the condition for enabling this bit, and\nalso make sure we set it at soon as we go over 104MHz.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\nThis is a port from Linux.\n---\n drivers/mtd/nand/spi/winbond.c | 13 ++++++++-----\n 1 file changed, 8 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c\nindex 79c3354efb65..accb46dfeb03 100644\n--- a/drivers/mtd/nand/spi/winbond.c\n+++ b/drivers/mtd/nand/spi/winbond.c\n@@ -261,16 +261,19 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spinand)\n \tu8 sr4;\n \tint ret;\n \n+\t/*\n+\t * SDR dual and quad I/O operations over 104MHz require the HS bit to\n+\t * enable a few more dummy cycles.\n+\t */\n \top = spinand->op_templates.read_cache;\n \tif (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)\n \t\ths = false;\n-\telse if (op->cmd.buswidth == 1 && op->addr.buswidth == 1 &&\n-\t\t op->dummy.buswidth == 1 && op->data.buswidth == 1)\n+\telse if (op->cmd.buswidth != 1 || op->addr.buswidth != 1)\n+\t\ths = false;\n+\telse if (op->max_freq && op->max_freq <= 104 * HZ_PER_MHZ)\n \t\ths = false;\n-\telse if (!op->max_freq)\n-\t\ths = true;\n \telse\n-\t\ths = false;\n+\t\ths = true;\n \n \tret = spinand_read_reg_op(spinand, W25N0XJW_SR4, &sr4);\n \tif (ret)\n", "prefixes": [ "3/3" ] }