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{ "id": 2231937, "url": "http://patchwork.ozlabs.org/api/1.1/covers/2231937/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/cover/20260501155421.3329862-1-elder@riscstar.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260501155421.3329862-1-elder@riscstar.com>", "date": "2026-05-01T15:54:08", "name": "[net-next,00/12] net: enable TC956x support", "submitter": { "id": 89551, "url": "http://patchwork.ozlabs.org/api/1.1/people/89551/?format=api", "name": "Alex Elder", "email": "elder@riscstar.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/cover/20260501155421.3329862-1-elder@riscstar.com/mbox/", "series": [ { "id": 502478, "url": "http://patchwork.ozlabs.org/api/1.1/series/502478/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502478", "date": "2026-05-01T15:54:09", "name": "net: enable TC956x support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502478/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2231937/comments/", "headers": { "Return-Path": "\n <linux-gpio+bounces-35952-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=riscstar-com.20251104.gappssmtp.com\n header.i=@riscstar-com.20251104.gappssmtp.com header.a=rsa-sha256\n header.s=20251104 header.b=uZUGjoJq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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This is an Ethernet-AVB/TSN bridge IC\nthat provides a high-speed connection between a host SoC and Ethernet\ndevices on a network. It incorporates a PCIe switch, and implements\ntwo 10 Gbps capable Ethernet MACs (along with other IP blocks), and\nis essentially a small and highly-specialized SoC. The TC9564 is a\nmember of a family of similar chips, and the driver code uses \"tc956x\"\nto reflect this.\n\nTC956x chips incorporate a PCIe gen 3 switch, with one upstream and\nthree downstream ports. Its PCIe functionality is already supported\nupstream, including a power control driver that performs some early\nconfiguration of the PCI ports (\"pci-pwrctrl-tc9563.c\").\n\nOne of the PCIe switch's downstream ports has an internal PCIe endpoint,\nwhich implements two PCIe functions, each of which has an Ethernet MAC\n(eMAC) subsystem. The eMAC is composed of a Synopsis Designware XGMAC\ncombined with an XPCS and PMA. Each MAC is capable of operating at\n10M/100M/1G/2.5G/5Gps and 10Gps. The initial target platform is the\nQualcomm RB3gen2, which supports a 10Gbps Marvell PHY on port A, and\na 2.5Gbps Qualcomm PHY on port B. (The Marvell PHY is not populated on\nall RB3gen2 boards, and only 2.5 Gbps support is included initially.)\n\nTC956x chips also implement several other blocks of functionality,\nincluding a GPIO controller, interrupt controllers (MSIGEN), I2C\nand SPI, a UART, and an Arm Cortex M3 CPU with 128KB SRAM. The GPIO\ninterface exposes several lines to manage external resets. The\ninterrupt controllers are used internally by the MAC functions. The\nUART, SPI, microcontroller, and SRAM are currently unused.\n\n ----------------------------------\n | Host |\n ------+...+----------+........+---\n |i2c| | PCIe |\n ----------------+...+----------+........+------\n | TC956x |I2C| |upstream| |\n | ----- --+--------+--- |\n | ----- ------ ------- | PCIe switch | |\n | |SPI| |GPIO| |reset| | | |\n | ----- ------ |clock| | DS3 DS2 DS1 | |\n | ------- ---++--++--++-- |\n | ----- ------ downstream// \\\\ \\\\ | downstream\n | |MCU| |SRAM| /==========/ \\\\ \\===== PCIe port 1\n | ----- ------ //PCIe port 3 \\\\ |\n | || \\======= downstream\n | ----+-----------++-----------+---- | PCIe port 2\n | | M | internal PCIe endpoint | M | |\n | | S |------------------------| S | ------ |\n | | I | PCIe | | PCIe | I | |UART| |\n | | G |function 0| |function 1| G | ------ |\n | | E |----++----| |----++----| E | |\n | | N | eMAC 0 | | eMAC 1 | N | |\n --------+.......+------+.....+-----------------\n |USXGMII| |SGMII|\n --+.......+-- --+.....+--\n | ARQ113C | | QEP8121 |\n | PHY | | PHY |\n ------------- -----------\n\nThe primary objective for this series is to support the Ethernet\nfunctionality provided by the TC956x. The code providing this\nsupport has been structured into three distinct modules.\n - A driver for the GPIO controller\n - Code enabling the TC956x-specific eMAC/MSIGEN hardware\n - A \"chip\" driver, associated with the PCIe functions\n\nThe GPIO driver is implemented separately because in some hardware\nconfigurations, these GPIO lines are used to manage resets for\nexternal Ethernet PHYs. We describe these PHYs via devicetree,\nwhere the GPIO-based reset signals are defined using phandles.\n\nThe code for the eMAC/MSIGEN consists of a new source file that\npopulates hardware-specific details about the two MACs, and integrates\nwith the existing stmmac driver. This also required implementing some\nenhancements to the core stmmac driver, described further below.\n\nTo manage the common functionality (including configuring address\ntranslation and controlling internal reset and clock signals), a\n\"chip\" driver is implemented. This chip driver is associated with\nthe PCIe function *itself*, not the eMAC associated with the function.\n\nThe driver binds to the internal PCI functions 0 and 1, and creates\na shared data structure describing the common chip elements the two\ndriver instances share. Three auxiliary bus devices are created to\nrepresent the GPIO controller and the two Synopsys MAC controllers.\n\nThe driver instance for PCIe function 0 has responsibility for\ncontrolling the common chip functionality--creating the GPIO\ncontroller auxiliary device, configuring address translation\nbetween PCIe address space and internal addresses, and controlling\nclocks and resets. It creates a data structure--shared via its\nplatform data pointer with PCIe function 1--to represent shared\n\"chip\" information. In addition, PCIe function 0 creates an\nauxiliary device to represent its attached eMAC. It allocates\nIRQs and maps BAR address ranges for use by the stmmac driver,\npassing them in a structure via the auxiliary device's platform\ndata.\n\nPCIe function 1 defers probing until after PCIe function 0 has\ncreated the shared data structure. After that its only job is\nto set up IRQs and mapped memory and create the eMAC1 auxiliary\ndevice.\n\nThe version of the Synopsys MAC IP is 3.01, which is largely compatible\nwith version 2.20. The core stmmac driver required several changes to\nenable support for the TC956x.\n - A change to dwxgmac2 support changes the interrupt mode when\n multi_msi_en is enabled.\n - While most support for version 3.01 simply uses the 2.20 code,\n an erratum related to the RX ring length is implemented for\n 3.01 DMA operations.\n - Having the PCIe device be separate from an auxiliarly device\n implementing the eMAC required allowing a distinct DMA device\n to be maintained for an stmmac interface.\n\nIn addition:\n - A new source file provides memory-mapped access to XPCS using\n regmap. The alignment of the TC956x MDIO registers aren't\n suitable for using simple MMIO.\n - Two additional XPCS changes are implemented that provides\n support for the XPCS as implemented in the TC956x.\n\nThis series is available here:\n https://github.com/riscstar/linux/tree/tc956x/stmmac-v1\n\n\t\t\t\t\t-Alex (and Daniel)\n\nAlex Elder (3):\n net: stmmac: dma: create a separate dma_device pointer\n gpio: tc956x: add TC956x/QPS615 support\n misc: tc956x_pci: add TC956x/QPS615 support\n\nDaniel Thompson (9):\n net: pcs: pcs-xpcs-regmap: support XPCS memory-mapped MDIO bus via\n regmap\n net: pcs: pcs-xpcs: select operating mode for 10G-baseR capable PCS\n net: pcs: pcs-xpcs: Preserve BMCR_ANENBLE during link up\n net: stmmac: dwxgmac2: Add multi MSI interrupt mode\n net: stmmac: dwxgmac2: Add XGMAC 3.01a support\n net: stmmac: dwxgmac2: export symbols for XGMAC 3.01a DMA\n dt-bindings: net: toshiba,tc965x-dwmac: add TC956x Ethernet bridge\n net: stmmac: tc956x: add TC956x/QPS615 support\n arm64: dts: qcom: qcs6490-rb3gen2: enable TC9564 with a single QCS8081\n phy\n\n .../bindings/net/toshiba,tc956x-dwmac.yaml | 111 +++\n arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 45 +-\n drivers/gpio/Kconfig | 11 +\n drivers/gpio/Makefile | 1 +\n drivers/gpio/gpio-tc956x.c | 209 +++++\n drivers/misc/Kconfig | 10 +\n drivers/misc/Makefile | 1 +\n drivers/misc/tc956x_pci.c | 667 +++++++++++++++\n drivers/net/ethernet/stmicro/stmmac/Kconfig | 13 +\n drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +\n .../net/ethernet/stmicro/stmmac/chain_mode.c | 12 +-\n .../ethernet/stmicro/stmmac/dwmac-tc956x.c | 791 ++++++++++++++++++\n .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 12 +\n .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 1 +\n .../ethernet/stmicro/stmmac/dwxgmac2_descs.c | 1 +\n .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 78 +-\n .../net/ethernet/stmicro/stmmac/ring_mode.c | 12 +-\n drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +\n .../net/ethernet/stmicro/stmmac/stmmac_main.c | 59 +-\n .../net/ethernet/stmicro/stmmac/stmmac_xdp.c | 2 +-\n drivers/net/pcs/Makefile | 4 +-\n drivers/net/pcs/pcs-xpcs-regmap.c | 203 +++++\n drivers/net/pcs/pcs-xpcs.c | 43 +-\n include/linux/pcs/pcs-xpcs-regmap.h | 20 +\n include/linux/stmmac.h | 1 +\n include/soc/toshiba/tc956x-dwmac.h | 84 ++\n 26 files changed, 2341 insertions(+), 53 deletions(-)\n create mode 100644 Documentation/devicetree/bindings/net/toshiba,tc956x-dwmac.yaml\n create mode 100644 drivers/gpio/gpio-tc956x.c\n create mode 100644 drivers/misc/tc956x_pci.c\n create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-tc956x.c\n create mode 100644 drivers/net/pcs/pcs-xpcs-regmap.c\n create mode 100644 include/linux/pcs/pcs-xpcs-regmap.h\n create mode 100644 include/soc/toshiba/tc956x-dwmac.h\n\n\nbase-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731" }