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{ "id": 2229692, "url": "http://patchwork.ozlabs.org/api/1.1/covers/2229692/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260428160103.3551125-1-jim.shu@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260428160103.3551125-1-jim.shu@sifive.com>", "date": "2026-04-28T16:00:59", "name": "[0/4] Minor fixes and enhancements of RISC-V AIA devices", "submitter": { "id": 83153, "url": "http://patchwork.ozlabs.org/api/1.1/people/83153/?format=api", "name": "Jim Shu", "email": "jim.shu@sifive.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260428160103.3551125-1-jim.shu@sifive.com/mbox/", "series": [ { "id": 501889, "url": "http://patchwork.ozlabs.org/api/1.1/series/501889/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501889", "date": "2026-04-28T16:01:00", "name": "Minor fixes and enhancements of RISC-V AIA devices", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501889/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2229692/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=nrbtPPiu;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pf1-x42a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Bugfix:\n - APLIC should also clear pending bit from rectified value when it is\n in the both level-trigger mode and direct delivery mode.\n\nEnhancements:\n - Add reset API to APLIC and IMSIC device\n - Add trace events of APLIC read/write function\n\nJim Shu (4):\n hw/intc: riscv_aplic: Fix level trigger IRQ in direct delivery mode\n hw/intc: riscv_aplic: Add reset API to APLIC\n hw/intc: riscv_imsic: Add reset API to IMSIC\n hw/intc: riscv_aplic: add trace events of APLIC read/write function\n\n hw/intc/riscv_aplic.c | 116 +++++++++++++++++++++++++++++-------------\n hw/intc/riscv_imsic.c | 19 +++++++\n hw/intc/trace-events | 4 ++\n 3 files changed, 105 insertions(+), 34 deletions(-)" }