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{ "id": 2229153, "url": "http://patchwork.ozlabs.org/api/1.1/covers/2229153/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260427181235.3003865-1-mhonap@nvidia.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260427181235.3003865-1-mhonap@nvidia.com>", "date": "2026-04-27T18:12:26", "name": "[RFC,0/9] QEMU: CXL Type-2 device passthrough via vfio-pci", "submitter": { "id": 92895, "url": "http://patchwork.ozlabs.org/api/1.1/people/92895/?format=api", "name": "Manish Honap", "email": "mhonap@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260427181235.3003865-1-mhonap@nvidia.com/mbox/", "series": [ { "id": 501717, "url": "http://patchwork.ozlabs.org/api/1.1/series/501717/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501717", "date": "2026-04-27T18:12:35", "name": "QEMU: CXL Type-2 device passthrough via vfio-pci", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501717/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2229153/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=rqg0/zc3;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "permerror client-ip=2a01:111:f403:c110::3;\n envelope-from=mhonap@nvidia.com;\n helo=BN8PR05CU002.outbound.protection.outlook.com" ], "From": "<mhonap@nvidia.com>", "To": "<alwilliamson@nvidia.com>, <skolothumtho@nvidia.com>, <ankita@nvidia.com>,\n <mst@redhat.com>, <imammedo@redhat.com>, <anisinha@redhat.com>,\n <eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <shannon.zhaosl@gmail.com>, <jonathan.cameron@huawei.com>,\n <fan.ni@samsung.com>, <pbonzini@redhat.com>, <richard.henderson@linaro.org>,\n <marcel.apfelbaum@gmail.com>, <clg@redhat.com>, <cohuck@redhat.com>,\n <dan.j.williams@intel.com>, <dave.jiang@intel.com>,\n <alejandro.lucero-palau@amd.com>", "CC": "<vsethi@nvidia.com>, <cjia@nvidia.com>, <targupta@nvidia.com>,\n <zhiw@nvidia.com>, <kjaju@nvidia.com>, <linux-cxl@vger.kernel.org>,\n <kvm@vger.kernel.org>, <qemu-devel@nongnu.org>, <qemu-arm@nongnu.org>,\n \"Manish Honap\" <mhonap@nvidia.com>", "Subject": "[RFC 0/9] QEMU: CXL Type-2 device passthrough via vfio-pci", "Date": "Mon, 27 Apr 2026 23:42:26 +0530", "Message-ID": "<20260427181235.3003865-1-mhonap@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.37]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FB:EE_|MN6PR12MB8542:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5d92f96d-b87b-42b7-c037-08dea488b5b0", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|7416014|376014|36860700016|82310400026|1800799024|921020|13003099007|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n PO9HMGXNRPzeKmpMW4lay998skO1hCp/hS6TjlQ067JjndmSdYGLSdPAuyngZoPZfzn8QJhZCu5bDLlVpx31eq78nEcnAt4SlkGJbKyOu4fu9fu6af0K0i2HFkkxXNQ19MJHdS69/9ivODUPC1enFwvHHh9Pz+Yd/YM6fJce0tJNxT5FCaKe+Lqy9xGTxZs4t/D+FGQXiX1YcEY3qFQ1a02THXxd+mci8oGoZZhTOPYrf5N7VUe/PW0F6O43Nz2EfrvpEoIbzHjUOQ0i9utxw5t5Esdu0Hn0POauPN5ImWZeZXVHEqGhILdY+thQqh8cLkvJ88T+LG0aK07sn0RuU1p0BnqB1E22s0CcRth4hh3sTWAYC9Auvks626aWQhZC62mkPNir0skqql2h07ZDxXnopA/qpJF220iUcq/TXSetnPwjYxX7FlRHMYo87bIV94R5mc5cPdRXEBc5NqCSeXc4xAjh5RKLxakNtnXm92lEByS3gMfbRWgjAVwOaiN3RbpaWM4OveoMMZ44zP0doTp7QSsRfIXOJ0OB5yL7INH7DDyQaH3lAw4Om+dUOjQuabqKRsEyQCM7+9WQzrFEmPigQtUejiYhJkGuT7JYg7OeW+TKVy7gysi+uzJDBLwyuwzAq8bWliJUaPkXvf35AVpjWID0EGt63TdmrUqHiS43uHUpg2vZANdNDNkY98YhF8eG57uOQcusCYL1XOxEjm2n2Rz3wTP5A3dd0BRLvnOWhQUSrb2Gr5KJYAzRzDwMO/uLIM1QpDz+JlikReY8u//pxZAVxrc31AUEZZBHPhKVmid2bmFKX8Knax8xb/IN", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230040)(7416014)(376014)(36860700016)(82310400026)(1800799024)(921020)(13003099007)(56012099003)(18002099003);\n DIR:OUT; SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n gGyGDS3SU+1gp6lAqF8lhBQh+K0jhSrpDMoy7wvw8i7e7rsxxVDd4Ry0UAoB3FKliPJV2fmNE/B377f46Lh171/GG/g2r5jYpZ3OsBADdiHphn4Z5JEiK6JBQ6UPypsXp+zONx5y6SWSNb0UNasUWTrI3ADsBhKlaL1fin4piUdAnT9weQCEqIiTU6k+z1pz2XXBgu53SQCyfRucFlePn3yPa9269oeUMdpKdnoi1d4CVoM7PJWzSz3T2oA8t4NcrLLBf5X2lOHMS3iPcyblC+PeTXJOfvFo5+/FUjwfKmk5m4yx7lT6DX4SgHg7yikApAtdDDvuIhh6qPrRMnO/lMPs1jgYbqeDL7kjnTtnb0nhu1ie3ouWsZx04OvhNL9rl2rkl+qc+oLrQZGnXAQg8TdkN6ZY8nxLe4qj6spwwC6MyhzngCt0I2u18t0vS/29", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "27 Apr 2026 18:13:40.1989 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5d92f96d-b87b-42b7-c037-08dea488b5b0", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A0FB.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN6PR12MB8542", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-Mailman-Approved-At": "Mon, 27 Apr 2026 15:57:41 -0400", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Manish Honap <mhonap@nvidia.com>\n\nThis series adds QEMU-side support for passing CXL Type-2 devices\n(GPUs and accelerators with host-managed device memory) to VMs via\nvfio-pci.\n\nIt pairs with the kernel series \"vfio/pci: CXL Type-2 passthrough\"[1]\nposted to the vfio mailing list. Patches 3-7 need that kernel series\npresent to do anything useful. I am new to QEMU development, so please\nforgive and point me in the right direction for correct infrastructure\ndecisions.\n\nBackground\n----------\n\nCXL Type-2 devices expose device memory (CXL.mem) through HDM decoders.\nThe kernel vfio-pci driver shadows the HDM Decoder Capability registers\nso userspace can observe and control decoder commits without touching\nthe hardware register page directly.\n\nWithout this series, the guest never sees the device memory range and\nthe HDM decoder goes unconfigured. The device shows up but its memory\nis unreachable.\n\nDesign decisions\n----------------\n\nCXL.mem is exposed to the guest as a dedicated GPA window declared in ACPI\n(CEDT/CFMWS) rather than a PCI BAR. The HDM decoder BASE must match the\nCFMWS base and remain stable; BAR assignment is not stable. A separate\nVIRT_HIGH_CXL_MMIO window in the ARM virt memory map carries this GPA range,\nindependent of the existing PCIe MMIO slots.\n\nThe Component Register BAR contains two distinct ranges. Accelerator\nregister windows are passed through as direct hardware mmaps via\nVFIO_REGION_INFO_CAP_SPARSE_MMAP. The HDM Decoder Capability block is\nexcluded from that sparse list by the kernel and must be intercepted by\nQEMU to track decoder state. A single priority-1 COMP_REGS overlay\nplaced at hdm_regs_offset inside the BAR container wins over any\nhardware-backed alias at the same offset, with no per-window aliasing\nrequired.\n\nThe guest has no mechanism to remap host physical mappings. QEMU programs\ndecoder 0 with the CFMWS base through the kernel's COMP_REGS shadow at\nmachine_done time, after all devices are realized and before the guest starts.\nThe notifier is registered only for devices the kernel reports as\nfirmware-committed (VFIO_CXL_CAP_FIRMWARE_COMMITTED).\n\nThe CXL.mem MemoryRegion is a mmap-backed RAM-device region backed by a\nVM_IO|VM_PFNMAP VMA. The VFIO MemoryListener would attempt an IOMMU\nDMA mapping for it when it is added to system_memory, which always\nfails: pin_user_pages() refuses VM_IO pages. No IOMMU mapping is needed\nfor these regions - CPU access goes via KVM Stage-2 page faults and\ndevice DMA to RAM uses separate per-RAM-section IOMMU entries. The\nlistener is extended to skip the mapping attempt for VFIO-owned\nRAM-device regions.\n\npxb-cxl bridges had no _DSM method. Without _DSM function 5 the OS\ndefaults to treating PCI configuration as reassignable.\nOn machines with firmware-committed HDM decoders that reassignment breaks\nthe CXL.mem mapping, so the _DSM is added with preserve_config=true for ARM and\nfalse for x86.\n\nKnown issues:\n- The bios-tables test will fail due to the _DSM addition.\n A fix will be provided in a follow-up round.\n- VFIO_CXL_CAP_CACHE_CAPABLE will require additional handling.\n- Devices with multiple firmware-committed HDM decoders are not fully\n supported.\n- Non-firmware-committed devices are not supported.\n- linux-headers sync is manual and temporary; once the kernel series is\n merged, this patch will be replaced with script generated update.\n\n[1] https://lore.kernel.org/linux-cxl/20260401143917.108413-1-mhonap@nvidia.com\n\nManish Honap (9):\n hw/arm/virt: Add CXL FMWS PA window for device memory\n cxl: Add preserve_config to pxb-cxl OSC method\n linux-headers: Update vfio.h for CXL Type-2 device passthrough\n hw/vfio/region: Add vfio_region_setup_with_ops() for custom region ops\n hw/vfio/pci: Add CXL Type-2 device detection and region setup\n hw/vfio/pci: Wire CXL component-register BAR with COMP_REGS overlay\n hw/vfio+cxl: Program HDM decoder 0 at machine_done for\n firmware-committed devices\n hw/arm/smmu-common: Allow pxb-cxl as SMMUv3 primary bus\n vfio/listener: Skip DMA mapping for VFIO-owned RAM-device regions\n\n hw/acpi/cxl-stub.c | 2 +-\n hw/acpi/cxl.c | 4 +-\n hw/arm/smmu-common.c | 17 +-\n hw/arm/virt-acpi-build.c | 5 +\n hw/arm/virt.c | 7 +\n hw/cxl/cxl-host-stubs.c | 2 +\n hw/cxl/cxl-host.c | 8 +\n hw/i386/acpi-build.c | 2 +-\n hw/pci-host/gpex-acpi.c | 43 +++-\n hw/vfio/listener.c | 14 ++\n hw/vfio/pci.c | 411 +++++++++++++++++++++++++++++++++++++\n hw/vfio/pci.h | 15 ++\n hw/vfio/region.c | 15 +-\n hw/vfio/trace-events | 6 +\n hw/vfio/vfio-region.h | 3 +\n include/hw/acpi/cxl.h | 2 +-\n include/hw/arm/virt.h | 2 +\n include/hw/cxl/cxl_host.h | 10 +\n include/hw/pci-host/gpex.h | 2 +\n linux-headers/linux/vfio.h | 18 ++\n 20 files changed, 570 insertions(+), 18 deletions(-)\n\n--\n2.25.1" }