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{
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    "project": {
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        "name": "Linux PCI development",
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    "msgid": "<cover.1777269009.git.nicolinc@nvidia.com>",
    "date": "2026-04-27T05:53:59",
    "name": "[v4,0/3] Allow ATS to be always on for certain ATS-capable devices",
    "submitter": {
        "id": 82183,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/82183/?format=api",
        "name": "Nicolin Chen",
        "email": "nicolinc@nvidia.com"
    },
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            "date": "2026-04-27T05:53:59",
            "name": "Allow ATS to be always on for certain ATS-capable devices",
            "version": 4,
            "mbox": "http://patchwork.ozlabs.org/series/501574/mbox/"
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        "From": "Nicolin Chen <nicolinc@nvidia.com>",
        "To": "<jgg@nvidia.com>, <will@kernel.org>, <robin.murphy@arm.com>,\n\t<bhelgaas@google.com>",
        "CC": "<joro@8bytes.org>, <praan@google.com>, <baolu.lu@linux.intel.com>,\n\t<kevin.tian@intel.com>, <miko.lenczewski@arm.com>,\n\t<linux-arm-kernel@lists.infradead.org>, <iommu@lists.linux.dev>,\n\t<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<dan.j.williams@intel.com>, <jonathan.cameron@huawei.com>,\n\t<vsethi@nvidia.com>, <linux-cxl@vger.kernel.org>, <nirmoyd@nvidia.com>",
        "Subject": "[PATCH v4 0/3] Allow ATS to be always on for certain ATS-capable\n devices",
        "Date": "Sun, 26 Apr 2026 22:53:59 -0700",
        "Message-ID": "<cover.1777269009.git.nicolinc@nvidia.com>",
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    "content": "PCI ATS function is controlled by the IOMMU driver calling pci_enable_ats()\nand pci_disable_ats() helpers. In general, IOMMU driver only enables ATS\nwhen a translation channel is enabled on a PASID, typically for an SVA use\ncase. When a device's RID is IOMMU bypassed and its PASIDs are not running\nSVA use case, ATS is always disabled.\n\nHowever, certain PCIe devices require non-PASID ATS on the RID, even if the\nRID is IOMMU bypassed. E.g. CXL.cache capability requires ATS to access the\nphysical memory; some pre-CXL NVIDIA GPUs also require the ATS to be always\non even when their RIDs are IOMMU bypassed.\n\nProvide a helper function to detect CXL.cache capability and scan through a\npre-CXL device ID list.\n\nAs the initial use case, call the helper in ARM SMMUv3 driver and adapt the\ndriver accordingly with a per-device ats_always_on flag.\n\nThis is on Github:\nhttps://github.com/nicolinc/iommufd/commits/pci_ats_always_on-v4/\n\nChangelog\nv4\n * Rebase on v7.1-rc1\n * Added Reviewed/Tested/Acked-by lines\n * Update commit messages and inline comments\n * [pci-quirks] Add range-based scan for NVIDIA GPUs\n * [smmu] Add missing arm_smmu_remove_master() in error path\n * [pci-ats] Don't init \"cap=0\"; check pci_read_config_word error\nv3\n https://lore.kernel.org/all/cover.1772833963.git.nicolinc@nvidia.com/\n * Add Reviewed-by from Jonathan\n * Update function kdocs of PCI APIs\n * Simplify boolean return/variable computations\nv2\n https://lore.kernel.org/all/cover.1771886695.git.nicolinc@nvidia.com/\n * s/non-CXL/pre-CXL\n * Rebase on v7.0-rc1\n * Update inline comments and commit message\n * Add WARN_ON back at !ptr in arm_smmu_clear_cd()\n * Add NVIDIA CX10 Family NVlink-C2C to the pre-CXL list\n * Do not add boolean parameter to arm_smmu_attach_dev_ste()\nv1\n https://lore.kernel.org/all/cover.1768624180.git.nicolinc@nvidia.com/\n\nNicolin Chen (3):\n  PCI: Allow ATS to be always on for CXL.cache capable devices\n  PCI: Allow ATS to be always on for pre-CXL devices\n  iommu/arm-smmu-v3: Allow ATS to be always on\n\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h |  1 +\n drivers/pci/pci.h                           |  9 +++\n include/linux/pci-ats.h                     |  3 +\n include/uapi/linux/pci_regs.h               |  1 +\n drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 75 ++++++++++++++++++---\n drivers/pci/ats.c                           | 44 ++++++++++++\n drivers/pci/quirks.c                        | 38 +++++++++++\n 7 files changed, 163 insertions(+), 8 deletions(-)"
}