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{ "id": 2227384, "url": "http://patchwork.ozlabs.org/api/1.1/covers/2227384/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/cover/20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com/", "project": { "id": 35, "url": "http://patchwork.ozlabs.org/api/1.1/projects/35/?format=api", "name": "Linux I2C development", "link_name": "linux-i2c", "list_id": "linux-i2c.vger.kernel.org", "list_email": "linux-i2c@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com>", "date": "2026-04-23T14:55:47", "name": "[v7,0/4] Enable multi-owner I2C support for QCOM GENI controllers", "submitter": { "id": 91179, "url": "http://patchwork.ozlabs.org/api/1.1/people/91179/?format=api", "name": "Mukesh Kumar Savaliya", "email": "mukesh.savaliya@oss.qualcomm.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-i2c/cover/20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com/mbox/", "series": [ { "id": 501206, "url": "http://patchwork.ozlabs.org/api/1.1/series/501206/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-i2c/list/?series=501206", "date": "2026-04-23T14:55:48", "name": "Enable multi-owner I2C support for QCOM GENI controllers", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/501206/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2227384/comments/", "headers": { "Return-Path": "\n <linux-i2c+bounces-17147-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-i2c@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=J/K3kKb9;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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Thu, 23 Apr 2026 20:27:13 +0530 (+0530)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1776956245; cv=none;\n b=orlAvKqHQvj8Kt/ZPCqEELV6cL470eo/YuS/+u8hZ1a7RucZKrjwpJUfhscZr1mqYhEWqk+PBrrGG682pvh9KdeeJ7W1sbJiZGLnK+lCwlIMz5H2DvnvLgE/wNf32hxkjKVTAVLmWhc0p4SUNN9IM+tlpWk75Tv4Xw9OQcM4s/U=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1776956245; c=relaxed/simple;\n\tbh=YO7uimmogf94fBti+r1q22cdT/6gxIiP2BRAF/hiPM0=;\n\th=From:To:Cc:Subject:Date:Message-ID:MIME-Version:Content-Type;\n b=i21pRSXy6PX8RDaZ5Gfdu3h9lBOXZ/JJYxCUaEbYTJakVXt5Vy4sKe6cHqjxN4r6DMhR8qHnIAW8Q+WgIm0KvUq0xNodCIdudxYUFXsTprFRmCu162FZSVFOgMl2Ae3CU0oYp8CP8YhoPxHZZmng1wUKyswVxbR1+RuLUzdzAMg=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com;\n spf=pass smtp.mailfrom=qualcomm.com;\n dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=J/K3kKb9; arc=none smtp.client-ip=205.220.180.131", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h=\n\tcc:content-transfer-encoding:content-type:date:from:message-id\n\t:mime-version:subject:to; s=qcppdkim1; bh=6lH8naoBlkskpbP8iT6CJp\n\txOKSSew15SkbohzS8SlLY=; b=J/K3kKb91JQhOEFy4E++aRSAlMTOkmgb0K6Td7\n\tRmM19Ee1Xzhdw7QcKcQe9/AP/DmGmQn3i9ZYW5O12qAlKXtEi9WWsrjoJKVDIDVc\n\tuRW+stXu5EV5hD1eDSs8hQGzmayIfCnuEn4894pc076Wyi6o3tnN3OSFYB5tOfOZ\n\tTxE5Wu+3gln7uf0H+bOKd1A4lP5rRfqh5PI2GUCEfhI0fWFp9RP5ZXLUnQXh1BRT\n\tMoMXx6Jk1BeAaMHl/NaSifFNCcupkqRxA73gjh48uNYWmpJT6CxdId38o1fkk2xe\n\t8x5D64JlcJIOGkILmB66zW4BCgHrih4JdMSn840smNWqIBbw==", "From": "Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>", "To": "viken.dadhaniya@oss.qualcomm.com, andi.shyti@kernel.org, robh@kernel.org,\n krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org,\n Frank.Li@kernel.org, andersson@kernel.org, konradybcio@kernel.org,\n dmitry.baryshkov@oss.qualcomm.com, linmq006@gmail.com,\n quic_jseerapu@quicinc.com, agross@kernel.org,\n linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n dmaengine@vger.kernel.org", "Cc": "krzysztof.kozlowski@oss.qualcomm.com,\n bartosz.golaszewski@oss.qualcomm.com,\n bjorn.andersson@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com,\n Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>", "Subject": "[PATCH v7 0/4] Enable multi-owner I2C support for QCOM GENI\n controllers", "Date": "Thu, 23 Apr 2026 20:25:47 +0530", "Message-ID": "<20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.43.0", "Precedence": "bulk", "X-Mailing-List": "linux-i2c@vger.kernel.org", "List-Id": "<linux-i2c.vger.kernel.org>", "List-Subscribe": "<mailto:linux-i2c+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-i2c+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-QCInternal": [ "smtphost", "smtphost" ], "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDIzMDE0OSBTYWx0ZWRfXy5lmkXxLWlLd\n BRhp8nrYGAzjIxsThiJwjJdrO+U86EC7j7H+gSmj74b89P39Dy5ian0gZDqhls0Gg5lPoGfHIsV\n vMffI2dj2KkdGJXQMmbMcnNgGfzG8QiPjsrWbvmrfTVcQK+c7JDhnPOKjLrUj3JgV6/CuWasObP\n Tccq+f9vz4qECJvVud1RfoAqieDq9OIC1BKsg/vOuIBUYpaGfVEfDe7phJOyFgXvrBEnI8NXydH\n fm+OFBOsGVwsu3GAyXVIFDvLXhqxpGjWGlnB2KV7MegFmqkeJpvKEbUGJje5cofrC4ZrNR2/fdB\n rrHdULuJgPBpqfsxn6cP8aiv60Hf9oOpvvaJScL7RcoojcvTijCY+8jy9gk0uR6oNlnmfCmWs6g\n Fn3SjXbR8jE/v6mokoUSkkSj02r2IdCTBx7ah5aMOQefjTSfkG7TOi52tlxZ8Rd5fa7yygK7yRV\n 0Qo9v6FoIX6OOCpXooA==", "X-Proofpoint-ORIG-GUID": "lPNHdrv6Cc5T2I-nN7ReFKYid907dH4X", "X-Proofpoint-GUID": "lPNHdrv6Cc5T2I-nN7ReFKYid907dH4X", "X-Authority-Analysis": "v=2.4 cv=TJt1jVla c=1 sm=1 tr=0 ts=69ea334f cx=c_pps\n a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8\n a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=hcHQekJc3wpFfe21-KYA:9 a=3ZKOabzyN94A:10\n a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n adultscore=0 spamscore=0 priorityscore=1501 phishscore=0 clxscore=1015\n malwarescore=0 bulkscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230149" }, "content": "The QUP-based GENI I2C controller driver currently assumes exclusive\nownership of the controller by a single system processor. This prevents\nsafe use of a single I2C controller by multiple system processors\n(e.g. APPS and a DSP) running the same or different operating systems.\n\nOne practical example is an EEPROM connected to an I2C controller that\nneeds to be accessed independently by firmware running on a DSP and by\nLinux running on the application processor, without causing bus-level\ninterference during transfers.\n\nThis series adds support for operating a QUP GENI I2C Serial Engine in a\nmulti-owner configuration. Each system processor uses its own dedicated\nGPI instance (GPII) as the data path between the Serial Engine and the\nGSI DMA engine. As a result, controller sharing is supported only when\nthe I2C controller operates in GPI mode; FIFO/CPU DMA modes are not\nsupported for this configuration.\n\nTo serialize access at the hardware level, the GPI DMA engine is used to\nemit lock and unlock Transfer Ring Elements (TREs) around I2C transfers.\nThe lock is acquired before the first transfer and released after the\nlast transfer, ensuring uninterrupted access to the controller while a\nprocessor owns it.\n\nIn addition, when a controller is shared, the GENI common layer avoids\nplacing the associated GPIOs into the pinctrl \"sleep\" state during\nruntime suspend. This prevents disruption of transfers that may still\nbe in progress on another system processor using the same controller\npins.\n\nThe multi-owner behavior is enabled via a DeviceTree property,\n`qcom,qup-multi-owner`, on the I2C controller node. This property must be\nused only when the hardware configuration requires controller sharing\nand when GPI mode is enabled.\n\nPatch overview:\n 1. Document the `qcom,qup-multi-owner` DeviceTree property for GENI I2C.\n 2. Extend the QCOM GPI DMA driver to support lock and unlock TREs with a\n simplified single-field API.\n 3. Update the GENI common layer to keep pinctrl active for shared\n controllers during runtime suspend.\n 4. Enable multi-owner operation in the GENI I2C driver using the new\n DeviceTree property and GPI lock/unlock support.\n\nSigned-off-by: Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com>\n\n---\nLink to V6 : https://lore.kernel.org/all/20260331114742.2896317-1-mukesh.savaliya@oss.qualcomm.com/\nChanges in V7:\n - Added Acked-by for dt-biding patch 1 given by Rob.\n - Minor description change for multi_owner variable in patch 3 and added RB tag from Konrad.\n - Removed description of multi_owner DT property from code as it's part of kernel doc.\n - Returned with dev_err_probe() in geni_i2c_probe() - Konrad's suggestion.\n\n\nLink to V5 : https://lore.kernel.org/lkml/20241129144357.2008465-2-mukesh.savaliya@oss.qualcomm.com/\nChanges in V6:\n - Addressed review feedback from Krzysztof Kozlowski and other reviewers, primarily\n around clarifying the feature semantics and improving the DeviceTree flag naming.\n - Renamed the DeviceTree property from qcom,shared-se to qcom,qup-multi-owner to\n better describe the multi-owner controller use case.\n - Updated the cover letter to clearly describe the multi-owner I2C design, the\n GPI-only limitation, and the role of the new qcom,qup-multi-owner flag.\n - Updated the DeviceTree binding documentation to reflect the new qcom,qup-multi-owner\n property and refined its description for clarity and correctness.\n - [Patch 2/4] Simplify the GPI I2C interface by replacing multiple shared SE related\n state flags with a single internal lock/unlock control managed entirely in the GPI\n driver - Suggested by Vinod Koul.\n - [Patch 3/4] Updated the GENI common layer to avoid selecting the pinctrl “sleep”\n state for multi-owner controllers, preventing disruption of transfers initiated by\n another system processor during runtime suspend.\n - [Patch 4/4] Updated the GENI I2C driver to: \n - Detect the qcom,qup-multi-owner DeviceTree property.\n\t- Mark the underlying serial engine as shared.\n\t- Request GPI lock and unlock TRE sequencing around I2C transfers using the\n\t simplified single field API.\n - Clarified commit messages across all patches to avoid ambiguous terminology\n (such as “subsystem”), expand abbreviations, and better explain functional\n requirements rather than optimizations.\n - Updated copyright headers across all files wherever applicable.\n - Renamed variable shared_geni_se to multi_owner to match the DT property naming.\n - Changed dev_err(print_log) during probe() to dev_err_probe().\n \n\nLink to V4 : https://lore.kernel.org/lkml/20241113161413.3821858-1-quic_msavaliy@quicinc.com/\nChanges in V5:\n - Corrected name as qcom,shared-se instead of qcom,is-shared.\n - Added description for the SE acronyms into yaml file and commit log.\n - Renamed TRE_I2C_UNLOCK to TRE_UNLOCK being generic.\n - Log an error and return if non GPI mode goes into shared usecase.\n\n\nLink to V3: https://lore.kernel.org/lkml/20240927063108.2773304-4-quic_msavaliy@quicinc.com/T/\nChanges in V4:\n - Fixed Typo to dt-bindings in subject line of PATCH 1.\n - Replaced SS (subsystem) as multiprocessor as per Bryan's suggestions.\n - Replied to Krzysztof's comments and replaced SS with Multiprocessor system.\n - Removed Abbreviations and also bullet point list from PATCH 1.\n - Changed feature flag name from qcom,shared-se to qcom,is-shared.\n - Removed bullet points from example of usecase and explained in paragraph.\n - Changed title suffix to dmaengine from dma for Patch 2.\n - Rename TRE_I2C_LOCK to TRE_LOCK in PATCH 2.\n - Enhanced comments about not modifying the pin states on shared SE for PATCH 3.\n - Enhanced shared_geni_se struct member explanation as per Bjorn's comment in PATCH 3.\n - Moved GPIO unconfiguration description from patch 4 to patch 3 as pointed by Bjorn.\n - Removed debug log which was unrelated to this feature change.\n - Added usecase exmaple of shared SE in commit log.\n\n\nLink to V2: https://lore.kernel.org/lkml/a88a16ff-3537-4396-b2ea-4ba02b4850e9@quicinc.com/T/\nChanges in V3:\n - Added missing maintainers which i forgot to add.\n - Add cover letter with description of SS and EE for dt-bindings patch.\n - Added acronyms expansion to commit log.\n - [PATCH v2 3/4] : Removed exported symbol geni_se_clks_off(). \n Instead added changes to bypass pinctrl sleep configuration from\n geni_se_resources_off() function.\n - Changed title name of [PATCH v2 3/4] to reflect the suggested changes.\n - [PATCH v2 4/4] kept geni_i2c_runtime_suspend() as is and removed \n explicit call to geni_se_clks_off().\n - Removed is_shared variable from i2c driver and instead used common \n shared_geni_se variable from qcom-geni-se.h so that other protocols\n can also extend for similar feature.\n - I2C driver log changed from dev_err() to dev_dbg() for timeout.\n - set gpi_mode = true if shared_geni_se is set for this usecase. Enhanced\n comments around code and commit log.\n\n\nLink to V1: https://lore.kernel.org/lkml/cb7613d0-586e-4089-a1b6-2405f4dc4883@quicinc.com/T/\nChanges in V2:\n - Enhanced commit log grammatically for PATCH v1 3/4 as suggested by Bryan.\n - Updated Cover letter along with acronyms expansion.\n - Added maintainers list from other subsystems for review, which was missing.\n Thanks to Krzysztof for pointing out.\n - Added cover letter with an example of Serial Engine sharing.\n - Addressed review comments for all the patches.\n---\nMukesh Kumar Savaliya (4):\n dt-bindings: i2c: qcom,i2c-geni: Document multi-owner controller\n support\n dmaengine: qcom: gpi: Add lock/unlock TREs for multi-owner I2C\n transfers\n soc: qcom: geni-se: Keep pinctrl active for multi-owner controllers\n i2c: qcom-geni: Support multi-owner controllers in GPI mode\n\n .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 7 +++\n drivers/dma/qcom/gpi.c | 44 ++++++++++++++++++-\n drivers/i2c/busses/i2c-qcom-geni.c | 22 +++++++++-\n drivers/soc/qcom/qcom-geni-se.c | 15 +++++--\n include/linux/dma/qcom-gpi-dma.h | 18 ++++++++\n include/linux/soc/qcom/geni-se.h | 2 +\n 6 files changed, 102 insertions(+), 6 deletions(-)" }