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{ "id": 2221599, "url": "http://patchwork.ozlabs.org/api/1.1/covers/2221599/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260409220614.65558-1-lucaaamaral@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260409220614.65558-1-lucaaamaral@gmail.com>", "date": "2026-04-09T22:06:08", "name": "[v6,0/6] target/arm: ISV=0 data abort emulation library", "submitter": { "id": 92822, "url": "http://patchwork.ozlabs.org/api/1.1/people/92822/?format=api", "name": "Lucas Amaral", "email": "lucaaamaral@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260409220614.65558-1-lucaaamaral@gmail.com/mbox/", "series": [ { "id": 499364, "url": "http://patchwork.ozlabs.org/api/1.1/series/499364/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=499364", "date": "2026-04-09T22:06:10", "name": "target/arm: ISV=0 data abort emulation library", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/499364/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2221599/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Bc9bKj2S;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::132c;\n envelope-from=lucaaamaral@gmail.com; helo=mail-dy1-x132c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add a shared emulation library for AArch64 load/store instructions that\ncause ISV=0 data aborts under hardware virtualization, and wire it into\nHVF (macOS) and WHPX (Windows).\n\nWhen the Instruction Syndrome Valid bit is clear, the hypervisor cannot\ndetermine the faulting instruction's target register or access size from\nthe syndrome alone. This previously hit an assert(isv) and killed the\nVM. The library fetches and decodes the faulting instruction using a\ndecodetree-generated decoder, then emulates it directly against the vCPU\nregister file and memory.\n\nThe library uses its own a64-ldst.decode rather than sharing\ntarget/arm/tcg/a64.decode — TCG's trans_* functions emit IR into a\ntranslation block, while this library's execute directly. Decode\npatterns are kept consistent with TCG's where possible; differences\nare noted in the relevant commit messages.\n\nChanges since v5:\n - Replace cpu_memory_rw_debug() with get_phys_addr() +\n address_space_read/write() for proper guest MMU translation\n instead of debug access path (Richard Henderson)\n - Handle page-crossing accesses via per-page chunked loop\n instead of rejecting them\n - Replace custom sign_extend() with sextract64() from\n qemu/bitops.h (Richard Henderson)\n - Remove unnecessary (void) casts (Richard Henderson)\n - Add guest endianness support: be_data flag with\n ldn_le_p/ldn_be_p byte-order-aware helpers instead of\n host-endian memcpy (Richard Henderson)\n\nChanges since v4:\n - Rebased onto current master\n - Add SPDX license identifier to new meson.build\n - Resent as new top-level thread (Alex Bennée)\n\nChanges since v3:\n - Document decodetree pattern differences from TCG in commit\n messages for patches 1/6 and 5/6.\n\nChanges since v2:\n - Inject synchronous external abort (matching kvm_inject_arm_sea()\n syndrome) on unhandled instruction or memory error, instead of\n silently advancing PC or returning an error.\n - Fix WHPX advance_pc bug: error paths no longer advance PC.\n - Add page-crossing guard in mem_read/mem_write to prevent partial\n side effects.\n\nChanges since v1:\n - Split monolithic patch into 6 incremental patches: framework, then\n one patch per coherent instruction group (Peter)\n - Removed per-backend callback ops; library uses CPUArchState directly\n for memory access (Mohamed)\n - Removed mock unit tests (Mohamed; kvm-unit-tests is the right\n vehicle for decoder validation)\n - Added architectural justification for separate decode file\n\nLucas Amaral (6):\n target/arm/emulate: add ISV=0 emulation library with load/store\n immediate\n target/arm/emulate: add load/store register offset\n target/arm/emulate: add load/store pair\n target/arm/emulate: add load/store exclusive\n target/arm/emulate: add atomic, compare-and-swap, and PAC load\n target/arm/hvf,whpx: wire ISV=0 emulation for data aborts\n\n target/arm/emulate/a64-ldst.decode | 293 +++++++++++\n target/arm/emulate/arm_emulate.c | 805 +++++++++++++++++++++++++++++\n target/arm/emulate/arm_emulate.h | 30 ++\n target/arm/emulate/meson.build | 8 +\n target/arm/hvf/hvf.c | 46 +-\n target/arm/meson.build | 1 +\n target/arm/whpx/whpx-all.c | 61 ++-\n 7 files changed, 1240 insertions(+), 4 deletions(-)\n create mode 100644 target/arm/emulate/a64-ldst.decode\n create mode 100644 target/arm/emulate/arm_emulate.c\n create mode 100644 target/arm/emulate/arm_emulate.h\n create mode 100644 target/arm/emulate/meson.build" }