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{ "id": 2221076, "url": "http://patchwork.ozlabs.org/api/1.1/covers/2221076/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/cover/20260408-jk-even-more-e825c-fixes-v1-0-b959da91a81f@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/1.1/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260408-jk-even-more-e825c-fixes-v1-0-b959da91a81f@intel.com>", "date": "2026-04-08T18:46:30", "name": "[iwl-net,0/4] ice: E825C missing PHY timestamp interrupt fixes", "submitter": { "id": 9784, "url": "http://patchwork.ozlabs.org/api/1.1/people/9784/?format=api", "name": "Jacob Keller", "email": "jacob.e.keller@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/cover/20260408-jk-even-more-e825c-fixes-v1-0-b959da91a81f@intel.com/mbox/", "series": [ { "id": 499189, "url": "http://patchwork.ozlabs.org/api/1.1/series/499189/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=499189", "date": "2026-04-08T18:46:30", "name": "ice: E825C missing PHY timestamp interrupt fixes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499189/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2221076/comments/", "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=y8IGFFKg;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::136; 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a=\"75841380\"", "E=Sophos;i=\"6.23,168,1770624000\"; d=\"scan'208\";a=\"75841380\"", "E=Sophos;i=\"6.23,168,1770624000\"; d=\"scan'208\";a=\"230217556\"" ], "X-ExtLoop1": "1", "From": "Jacob Keller <jacob.e.keller@intel.com>", "Date": "Wed, 08 Apr 2026 11:46:30 -0700", "Message-Id": "<20260408-jk-even-more-e825c-fixes-v1-0-b959da91a81f@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "X-B4-Tracking": "v=1; b=H4sIAAAAAAAC/yWMwQ6CMBAFf4Xs2U3aqhX9FeMB2qcuaiFdRBPCv\n 1v1OJnMzKTIAqVDNVPGJCp9KmBXFYVrky5giYXJGefNxtTc3RgTEj/6DEbttoHP8obyvvEx7tb\n WttFTyYeMnyj1keR154SRTn+hz7ZDGL9jWpYPd7f0hYUAAAA=", "X-Change-ID": "20260408-jk-even-more-e825c-fixes-9a6dd7311bd6", "To": "Anthony Nguyen <anthony.l.nguyen@intel.com>,\n Intel Wired LAN <intel-wired-lan@lists.osuosl.org>, netdev@vger.kernel.org", "X-Mailer": "b4 0.16-dev-306a9", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=5658;\n i=jacob.e.keller@intel.com; h=from:subject:message-id;\n bh=DmanvA9tHclxyhu+ESIggN6Ege+JBj0Mde5bEHp/2x4=;\n b=owGbwMvMwCWWNS3WLp9f4wXjabUkhsxri9Y2zNOprTy0fNsH8WWHGr5d2lfzKzEqbdL8A4cXv\n 9Oy/7m9rqOUhUGMi0FWTJFFwSFk5XXjCWFab5zlYOawMoEMYeDiFICJtDxhZFj3nL9eqvp45pY7\n 04rfzf5RWT910+u0k6zLO1xe15w+r7qS4X9AtWrVQlnp2zlyiX5s3pE8h4VePQnpVtMoeiCrqHh\n vDzcA", "X-Developer-Key": "i=jacob.e.keller@intel.com; a=openpgp;\n fpr=204054A9D73390562AEC431E6A965D3E6F0F28E8", "X-Mailman-Original-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1775674048; x=1807210048;\n h=from:subject:date:message-id:mime-version:\n content-transfer-encoding:to:cc;\n bh=DmanvA9tHclxyhu+ESIggN6Ege+JBj0Mde5bEHp/2x4=;\n b=dnNFVpDGQxWyStU46fIMsG5aB/yjiwCWM6Y2m+FbqRWsYnoiZao/rC8D\n zjvUaGaK8tF3s1j06iztpsK1lmgb03vc0rYGnHAe2CIN1CzDjCZXZdi/4\n 0WdrkXKRZMxJrET5KZto9vhxW4WvGIP9dtcRyrYnlMo3LI1rMNtx91Dcn\n N+CRfX8hpEYHsBRxjMTLrP8F0ISoeNHiZCTxGZ2bNAVpxSw49/mvhZHUn\n EOxL7bJo7474wV4RIYAWp4IK88NmN9gNpNWG1pYiRbZgKpf0NviwCRRqq\n MziXdUsSMTELnHr6HnBM2YUXVmjsOxUZqX+PcfXtYvT3ZswuNuLwr5yJN\n A==;", "X-Mailman-Original-Authentication-Results": [ "smtp3.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com", "smtp3.osuosl.org;\n dkim=pass (2048-bit key,\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=dnNFVpDG" ], "Subject": "[Intel-wired-lan] [PATCH iwl-net 0/4] ice: E825C missing PHY\n timestamp interrupt fixes", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "Aleksandr Loktionov <aleksandr.loktionov@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>,\n Timothy Miskell <timothy.miskell@intel.com>", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "We recently ran into a nasty corner case issue with a customer operating\nE825C cards seeing some strange behavior with missing Tx timestamps. During\nthe course of debugging. This series contains a few fixes found during this\ndebugging process.\n\nThe primary issue discovered in the investigation is a misconfiguration of\nthe E825C PHY timestamp interrupt register, PHY_REG_TS_INT_CONFIG. This\nregister is responsible for programming the Tx timestamp behavior of a PHY\nport. The driver programs two values here: a threshold for when to\ninterrupt and whether the interrupt is enabled.\n\nThe threshold value is used by hardware to determine when to trigger a Tx\ntimestamp interrupt. The interrupt cause for the port is raised when the\nnumber of outstanding timestamps in the PHY port timestamp memory meets the\nthreshold. The interrupt cause is not cleared until the number of\noutstanding timestamps drops *below* the threshold.\n\nIt is considered a misconfiguration if the threshold is programmed to 0. If\nthe interrupt is enabled while the threshold is zero, hardware will raise\nthe interrupt cause at the next time it checks. Once raised, the interrupt\ncause for the port will never lower, since you cannot have fewer than zero\noutstanding timestamps.\n\nWorse, the timestamp status for the port will remain high even if the\nPHY_REG_TS_INT_CONFIG is reprogrammed with a new threshold. The PHY is a\nseparate hardware block from the MAC, and thus the interrupt status for the\nport will remain high even if you reset the device MAC with a PF reset,\nCORE reset, or GLOBAL reset.\n\nPHY ports are connected together into quads. Each quad muxes the PHY\ninterrupt status for the 4 ports on the quad together before connecting\nthat to the MACs miscellaneous interrupt vector. As a result, if a single\nPHY port in the quad is stuck, no timestamp interrupts will be generated\nfor any timestamp on any port on that quad.\n\nThe ice driver never directly writes a value of 0 for the threshold.\nIndeed, the desired behavior is to set the threshold to 1, so that\ninterrupts are generated as soon as a single timestamp is captured.\nUnfortunately, it turns out that for the E825C PHY, programming the\nthreshold and enable bit in the same write may cause a race in the PHY\ntimestamp block. The PHY may \"see\" the interrupt as enabled first before it\nsees the threshold value. If the previous threshold value is zero (such as\nwhen the register is initialized to zero at a cold power on), the hardware\nmay race with programming the threshold and set the PHY interrupt status to\nhigh as described above.\n\nThe first patch in this series corrects that programming order, ensuring\nthat the threshold is always written first in a separate transaction from\nenabling the interrupt bit. Additionally, an explicit check against writing\na 0 is added to make it clear to future readers that writing 0 to the\nthreshold while enabling the interrupt is not safe.\n\nThe PHY timestamp block does not reset with the MAC, and seems to only\nreset during cold power on. This makes recovery from the faulty\nconfiguration difficult. To address this, perform an explicit reset of the\nPHY PTP block during initialization. This is achieved by writing the\nPHY_REG_GLOBAL register. This performs a PHY soft reset, which completely\nresets the timestamp block. This includes clearing the timestamp memory,\nthe PHY timestamp interrupt status, and the PHY PTP counter. A soft reset\nof all ports on the device is done as part of ice_ptp_init_phc() during\nearly initialization of the PTP functionality by the PTP clock owner, prior\nto programming each PHY. The ice_ptp_init_phc() function is called at\ndriver init and during reinitialization after all forms of device reset.\nThis ensures that the driver begins operation at a clean slate, rather than\ncarrying over the stale and potentially buggy configuration of a previous\ndriver.\n\nWhile attempting to root cause the issue with the PHY timestamp interrupt,\nwe also discovered that the driver incorrectly assumes that it is operating\non E822 hardware when reading the PHY timestamp memory status registers in\na few places. This includes the check at the end of the interrupt handler,\nas well as the check done inside the PTP auxiliary function. This prevented\nthe driver from detecting waiting timestamps on ports other than the first\ntwo.\n\nFinally, the ice_ptp_read_tx_hwstamp_status_eth56g() function was\ndiscovered to only read the timestamp interrupt status value from the first\nquad due to mistaking the port index for a PHY quad index. This resulted in\nreporting the timestamp status for the second quad as identical to the\nfirst quad instead of properly reporting its value. This is a minor fix\nsince the function currently is only used for diagnostic purposes and does\nnot impact driver decision logic.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\n---\nGrzegorz Nitka (2):\n ice: fix timestamp interrupt configuration for E825C\n ice: perform PHY soft reset for E825C ports at initialization\n\nJacob Keller (2):\n ice: fix ready bitmap check for non-E822 devices\n ice: fix ice_ptp_read_tx_hwtstamp_status_eth56g\n\n drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 5 +\n drivers/net/ethernet/intel/ice/ice_ptp.c | 40 ++---\n drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 253 +++++++++++++++++++++++++++-\n 3 files changed, 265 insertions(+), 33 deletions(-)\n---\nbase-commit: e3b6e4778608889866917014b7dfe88425073fe5\nchange-id: 20260408-jk-even-more-e825c-fixes-9a6dd7311bd6\n\nBest regards,\n-- \nJacob Keller <jacob.e.keller@intel.com>" }