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{ "id": 2220317, "url": "http://patchwork.ozlabs.org/api/1.1/covers/2220317/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/cover/20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com/", "project": { "id": 38, "url": "http://patchwork.ozlabs.org/api/1.1/projects/38/?format=api", "name": "Linux PWM development", "link_name": "linux-pwm", "list_id": "linux-pwm.vger.kernel.org", "list_email": "linux-pwm@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com>", "date": "2026-04-06T20:24:37", "name": "[v21,0/6] Add PWM support for IPQ chipsets", "submitter": { "id": 90538, "url": "http://patchwork.ozlabs.org/api/1.1/people/90538/?format=api", "name": "George Moussalem via B4 Relay", "email": "devnull+george.moussalem.outlook.com@kernel.org" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pwm/cover/20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com/mbox/", "series": [ { "id": 498895, "url": "http://patchwork.ozlabs.org/api/1.1/series/498895/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pwm/list/?series=498895", "date": "2026-04-06T20:24:40", "name": "Add PWM support for IPQ chipsets", "version": 21, "mbox": "http://patchwork.ozlabs.org/series/498895/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2220317/comments/", "headers": { "Return-Path": "\n <linux-pwm+bounces-8502-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pwm@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=FgBx1ekO;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775507137; cv=none;\n b=nktYEINRcTvzH00eB4z55ulyLimgpogkGEwBWDTLyiHD3luTUO38kcaxObz3pAMCWtWUYf2eSiI/TW5Jc66Ojx1AkPIO8F4eEk4zh+5AKLxCHOYVjwHSUJG/b5nE9WfvtAeKeHKLeVpzwkztmhj9xOw3k6F40vwqPxNtP2MK7kM=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775507137; c=relaxed/simple;\n\tbh=SDhHc8Gdlrhgi2kS2fCmPzPir3jVgVnkcwYGV6/fk9M=;\n\th=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc;\n b=nW58hFznvZeDe45S6pal+85BPFcdpquPQczCCMpXTgZwdC8pn7VG3WdPcLFSsNlrm57f+4fqlJMNXkAyf9lwKg2V+Xnk0z1VbSuYpGT3VQ0HNANM3cRVz9JVR0DSmgH5PGzqKa1ueZ/pbM6PlQsmr6kL/QRBvcHcLFgmaR0SlQM=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=FgBx1ekO; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775507137;\n\tbh=SDhHc8Gdlrhgi2kS2fCmPzPir3jVgVnkcwYGV6/fk9M=;\n\th=From:Subject:Date:To:Cc:Reply-To:From;\n\tb=FgBx1ekOUTiEsWsUrAoqOOdI/IWsOCVAScIt2qcejLH9Pj0ziRhibBhStbzF6O6QM\n\t j/vGVVgblX9bfnBuRJDjPNZa88To1XUTZP4k9HjPYTZ2CXNuiHixvrBOX9DXRB2OFk\n\t puq1gFoHX6TRe1hEU0dfcRBS3zkF9bOFvKmQvnnfvJBrjx2va5MCPz4p+IUgsnPXp5\n\t UVNMf7f9jTPcqczljd5qrkBkSHkOaGeso6fYsjffhsih4YlhEld1SXbbmpQu71/5y+\n\t gZsUsrdtlD4N7V020P/9hXD4rYbXri8nfC/Xtr3xRLnaBpi2bdl8Wn1OLSLBQe3qCV\n\t +0hzdgksoIs/g==", "From": "George Moussalem via B4 Relay\n <devnull+george.moussalem.outlook.com@kernel.org>", "Subject": "[PATCH v21 0/6] Add PWM support for IPQ chipsets", "Date": "Mon, 06 Apr 2026 22:24:37 +0200", "Message-Id": "<20260406-ipq-pwm-v21-0-6ed1e868e4c2@outlook.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pwm@vger.kernel.org", "List-Id": "<linux-pwm.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pwm+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pwm+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "X-B4-Tracking": "v=1; b=H4sIAIUW1GkC/23O0U7DMAwF0F+Z+kwm22malKf9B0KoTRwWQZcu3\n QrT1H8nrTRWxB6d+FzfazFwCjwUz5trkXgMQ4iHPBA+bQq7bw7vLILLDwUBKaiJROiPov/qhDV\n WK4uldoqKvN0n9uF7iXp5zbNPsROnfeLm5iUCKKxAKdhSSRK0EiiO52DfXD7dp3DZzVM42K2N3\n Ry6D8MppstSb8Rqzl6a5CT8bZI/BAgJ4ElqBq7MLp5PnzF+LDFzmRH12pqV1dnWrSslO2+11w+\n sWVmqV9Zky65lb9i3reEHtr5bpPXdOluUrdVQWls16r8luNkKCMq7JZg7o5YSEBvp8K+dpukHU\n CXzXtgBAAA=", "X-Change-ID": "20250922-ipq-pwm-c8c75c147d52", "To": "=?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,\n Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Bjorn Andersson <andersson@kernel.org>,\n Konrad Dybcio <konradybcio@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-pwm@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n George Moussalem <george.moussalem@outlook.com>,\n Devi Priya <quic_devipriy@quicinc.com>,\n Baruch Siach <baruch.siach@siklu.com>,\n Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,\n Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,\n Bjorn Andersson <andersson@kernel.org>,\n Krzysztof Kozlowski <krzk@kernel.org>", "X-Mailer": "b4 0.15.1", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775507135; l=6465;\n i=george.moussalem@outlook.com; s=20260406; h=from:subject:message-id;\n bh=SDhHc8Gdlrhgi2kS2fCmPzPir3jVgVnkcwYGV6/fk9M=;\n b=3JWHAb2VwyMun5FJ77dftxXSowjvRhsNsVjt17VuQmMMMLEZFy8r7ueQeWewK2OLqnScZg2nh\n KbGnOSdD2R7AOkqDVyp9wzw3F+8kVUYIL8kGu794NbXzZ5C5OHuwPuP", "X-Developer-Key": "i=george.moussalem@outlook.com; a=ed25519;\n pk=uqspem3ahtBvPEBuxVbyyXT/0Vp3JNb/mo1EPbmBzWg=", "X-Endpoint-Received": "by B4 Relay for george.moussalem@outlook.com/20260406\n with auth_id=722", "X-Original-From": "George Moussalem <george.moussalem@outlook.com>", "Reply-To": "george.moussalem@outlook.com" }, "content": "Add PWM driver and binding support for IPQ chipsets.\nAlso, add nodes to add support for pwm in ipq6018, ipq5018, ipq5332, and\nipq9574.\n\nI've picked up work based on Devi's last submission (v15) which dates\nback to 05 October 2023 as below SoCs are still active.\n\nSigned-off-by: George Moussalem <george.moussalem@outlook.com>\n---\nChanges in v21:\n- Added macro definition for minimum supported period and lower bound check to ensure a valid period \n- Added code comment to explain why pre_div won't overflow\n- Link to v20: https://patch.msgid.link/20260204-ipq-pwm-v20-0-91733011a3d1@outlook.com\n\nChanges in v20:\n- Updated IPQ_PWM_MAX_DIV macro definition to use FIELD_MAX\n- Removed clk struct from ipq_pwm struct and added clk_rate field\n instead which is set during probe.\n- Consolidated config_div_and_duty into ipq_pwm_apply\n- Fixed arithmetic overflows in apply and get_state\n- Fixed off-by-one in divider calculation\n- Enabled 100% relative duty cycle support\n- Aligned continuation on next lines relative to opening parentheses\n- Return 0 instead of ret in probe\n- Link to v19: https://lore.kernel.org/r/20251128-ipq-pwm-v19-0-13bc704cc6a5@outlook.com\n\nChanges in v19:\n- Changed pwm-cells property in dt bindings from 2 to 3 as per Uwe's\n recommendation\n- Added hardware notes and limitations based on own findings as\n requested. NOTE: there's no publically available datasheet though.\n- Expanded comment on REG1_UPDATE to indicate that when this bit is set,\n values for div and pre-div take effect. The hardware automatically\n unsets it when the change is completed.\n- Added newline between MACRO definition and next comment\n- In config_div_and_duty, used mul_u64_u64_div_u64 to avoid overflow\n- Removed unncessary restriction of pwm_div to MAX_DIV - 1 after testing\n- Constrain pre_div to MAX_DIV is pre_div calculated is > MAX_DIV\n- Use of mul_u64_u64_div_u64 in .apply\n- Skip calculation of period and duty cycle when PWM_ENABLE REG is unset\n- Set duty cycle to period value when calculated duty cycle > period to\n return a valid config\n- Removed .npwm as it's taken care of in devm_pwmchip_alloc\n- Added call to devm_clk_rate_exclusive_get to lock the clock rate\n- Start all kernel messages with a capital letter and end with \\n.\n- Changed pwm-cells property in all dtsi from 2->3 for in scope IPQ SOCs\n- Link to v18: https://lore.kernel.org/r/20251029-ipq-pwm-v18-0-edbef8efbb8e@outlook.com\n\nChanges in v18:\n- Updated maintainer info in binding\n- Squashed dt bindings patches into the first for adding compatibles for\n IPQ5018, IPQ5332, and IPQ9574\n- Link to v17: https://lore.kernel.org/r/20251008-ipq-pwm-v17-0-9bd43edfc7f7@outlook.com\n\nChanges in v17:\n- Picked up RB tags from Dmitry and Rob\n- Removed unnecessary code comments\n- Corrected reg property in PWM node in ipq6018 DTS in line with\n expected nr of bytes for address and size cells\n- Link to v16: https://lore.kernel.org/r/20251001-ipq-pwm-v16-0-300f237e0e68@outlook.com\n\nChanges in v16:\n- Removed reg description in bindings as the offset is not relative to\n the TCSR region anymore since simple-mfd support was dropped and PWM\n nodes defined as their own nodes, not child nodes. Updated the example\n too.\n- Dropped patch to add simple-mfd support to the qcom,tcsr bindings\n- Simplified code to calculate divs and duty cycle as per Uwe's comments\n- Removed unused pwm_chip struct from ipq_pwm_chip struct\n- Removed unnecessary cast as per Uwe's comment\n- Replaced devm_clk_get & clk_prepare_enable by devm_clk_get_enabled\n- Replaced pwmchip_add by devm_pwmchip_add and removed .remove function\n- Removed .owner from driver struct\n- Added compatibles to the bindings and nodes to the device trees to add\n PWM support in the IPQ5018, IPQ5332, and IPQ9574 SoCs\n- Link to v15: https://lore.kernel.org/r/20231005160550.2423075-1-quic_devipriy@quicinc.com\n\nChanges in v15:\n- No change\n- Link to v14: https://lore.kernel.org/r/20231005033053.2626465-1-quic_devipriy@quicinc.com\n\nChanges in v14:\n- Picked up the R-b tag\n- Link to v13: https://lore.kernel.org/r/20231004090449.256229-1-quic_devipriy@quicinc.com\n\nChanges in v13:\n- Updated the file name to match the compatible\n- Sorted the properties and updated the order in the required field\n- Dropped the syscon node from examples\n- Link to v12: https://lore.kernel.org/r/20230925065915.3467964-1-quic_devipriy@quicinc.com\n\nChanges in v12:\n- Picked up the R-b tag\n\nChanges in v11:\n- No change\n\nChanges in v10:\n- No change\n\nChanges in v9:\n- Add 'ranges' property to example (Rob)\n- Drop label in example (Rob)\n\nChanges in v8:\n- Add size cell to 'reg' (Rob)\n\nChanges in v7:\n- Use 'reg' instead of 'offset' (Rob)\n- Drop 'clock-names' and 'assigned-clock*' (Bjorn)\n- Use single cell address/size in example node (Bjorn)\n- Move '#pwm-cells' lower in example node (Bjorn)\n- List 'reg' as required\n\nChanges in v6:\n- Device node is child of TCSR; remove phandle (Rob Herring)\n- Add assigned-clocks/assigned-clock-rates (Uwe Kleine-König)\n\nChanges in v5:\n- Use qcom,pwm-regs for phandle instead of direct regs (Bjorn\n Andersson, Kathiravan T)\n\nChanges in v4:\n- Update the binding example node as well (Rob Herring's bot)\n\nChanges in v3:\n- s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring)\n\nChanges in v2:\n- Make #pwm-cells const (Rob Herring)\n\n---\n\n---\nDevi Priya (3):\n dt-bindings: pwm: add IPQ6018 binding\n pwm: driver for qualcomm ipq6018 pwm block\n arm64: dts: qcom: ipq6018: add pwm node\n\nGeorge Moussalem (3):\n arm64: dts: qcom: ipq5018: add pwm node\n arm64: dts: qcom: ipq5332: add pwm node\n arm64: dts: qcom: ipq9574: add pwm node\n\n .../devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml | 51 ++++\n arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 +\n arch/arm64/boot/dts/qcom/ipq5332.dtsi | 10 +\n arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 +\n arch/arm64/boot/dts/qcom/ipq9574.dtsi | 10 +\n drivers/pwm/Kconfig | 12 +\n drivers/pwm/Makefile | 1 +\n drivers/pwm/pwm-ipq.c | 259 +++++++++++++++++++++\n 8 files changed, 363 insertions(+)\n---\nbase-commit: 2febe6e6ee6e34c7754eff3c4d81aa7b0dcb7979\nchange-id: 20250922-ipq-pwm-c8c75c147d52\n\nBest regards,\n-- \nGeorge Moussalem <george.moussalem@outlook.com>" }