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GET /api/1.0/patches/2223053/?format=api
{ "id": 2223053, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2223053/?format=api", "project": { "id": 57, "url": "http://patchwork.ozlabs.org/api/1.0/projects/57/?format=api", "name": "Linux ASPEED SoC development", "link_name": "linux-aspeed", "list_id": "linux-aspeed.lists.ozlabs.org", "list_email": "linux-aspeed@lists.ozlabs.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260414-upstream_pinctrl-v6-2-709f2127da33@aspeedtech.com>", "date": "2026-04-14T09:39:00", "name": "[v6,2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe AST2700 SCU0", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "294b9c0e37b485975f137b5ed5e794040a26302a", "submitter": { "id": 80235, "url": "http://patchwork.ozlabs.org/api/1.0/people/80235/?format=api", "name": "Billy Tsai", "email": "billy_tsai@aspeedtech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20260414-upstream_pinctrl-v6-2-709f2127da33@aspeedtech.com/mbox/", "series": [ { "id": 499806, "url": "http://patchwork.ozlabs.org/api/1.0/series/499806/?format=api", "date": "2026-04-14T09:38:58", "name": "pinctrl: aspeed: Add AST2700 SoC0 support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/499806/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2223053/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-aspeed+bounces-3897-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; helo=lists.ozlabs.org;\n envelope-from=linux-aspeed+bounces-3897-incoming=patchwork.ozlabs.org@lists.ozlabs.org;\n receiver=patchwork.ozlabs.org)", "lists.ozlabs.org;\n arc=none smtp.remote-ip=211.20.114.72", "lists.ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com", "lists.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com\n (client-ip=211.20.114.72; helo=twmbx01.aspeed.com;\n envelope-from=billy_tsai@aspeedtech.com; receiver=lists.ozlabs.org)" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org\n [IPv6:2404:9400:21b9:f100::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1 raw public key)\n server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvzlW0Z6Xz1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 14 Apr 2026 19:40:07 +1000 (AEST)", "from boromir.ozlabs.org (localhost [127.0.0.1])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4fvzkx3bsBz2yvF;\n\tTue, 14 Apr 2026 19:39:37 +1000 (AEST)", "from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 4fvzkw3t5Zz2ytV;\n\tTue, 14 Apr 2026 19:39:36 +1000 (AEST)", "from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Tue, 14 Apr\n 2026 17:39:15 +0800", "from [127.0.1.1] (192.168.10.13) by TWMBX01.aspeed.com\n (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend\n Transport; Tue, 14 Apr 2026 17:39:15 +0800" ], "ARC-Seal": "i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1776159577;\n\tcv=none;\n b=jt84tEEEZoQuTJ4nh7E6AE9xBIMsDY4se0+dwVaRmHGIbVginE65DKwCu6EO46egj4oTbvcTcUcysUz36MIBJKJFTC1b+YjcxPTzZ2kfQVyYyIvWo2T6rZaEtW0JQANJ15RuDeyz0H8G3QhiKQU+rzu3fPTdAshpHlsnfU2qbj30uSd8qdBZ63SccJ/URRAbzA8G/f7qcid+HiuhVkJ9oM5+8i1Qtg/QVWvi7qFjTPaHfBbphtoNBu6Ni28xEzDs49Qk2sxFOcsQdaXDkxugXmf8kDE5dvBfLNl7AygGfZUTz+gUXvF0dn+A/t5Rxo369BLx5cTda54dNYnfTBuEiA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707;\n\tt=1776159577; c=relaxed/relaxed;\n\tbh=9jmhx+O3Xungi7P4kUQEmJk8LBfALKoeJZDCx8Q21QA=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References:\n\t In-Reply-To:To:CC;\n b=AkkauH6SsHTt8vwWHMeZO3D7aB1P0yhDfyGEHTdA1eLkKTcgGV/cgWpC7/qX7s5AJeyRJCAXrEeupqKDbbrdHlPqKM6j37GquzQlJDV8RCkvEJNujzGPD/cdCVJe0V86ZJNG0Iz2Z+kRA+y8aLJ0V1sEuo3HPEuzAGsvv7cRMDZqevzAZV1tDZGgpi2dBC3+CUMR48ufkXGc99bqBrgAc0Krg9A2YI4s12jNxKu1clrzxrUAqdcUisJwU0dCXSzdh7hBDQN5V6fxKPiIftXn/t63oBWC93d1S1VExu9e82jk8YagEnfouo7c9cLtGOHnjQ5jpa7Itzq8VVa1lbcT9g==", "ARC-Authentication-Results": "i=1; lists.ozlabs.org;\n dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com;\n spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com;\n envelope-from=billy_tsai@aspeedtech.com;\n receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com", "From": "Billy Tsai <billy_tsai@aspeedtech.com>", "Date": "Tue, 14 Apr 2026 17:39:00 +0800", "Subject": "[PATCH v6 2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe\n AST2700 SCU0", "X-Mailing-List": "linux-aspeed@lists.ozlabs.org", "List-Id": "<linux-aspeed.lists.ozlabs.org>", "List-Help": "<mailto:linux-aspeed+help@lists.ozlabs.org>", "List-Owner": "<mailto:linux-aspeed+owner@lists.ozlabs.org>", "List-Post": "<mailto:linux-aspeed@lists.ozlabs.org>", "List-Archive": "<https://lore.kernel.org/linux-aspeed/>,\n <https://lists.ozlabs.org/pipermail/linux-aspeed/>", "List-Subscribe": "<mailto:linux-aspeed+subscribe@lists.ozlabs.org>,\n <mailto:linux-aspeed+subscribe-digest@lists.ozlabs.org>,\n <mailto:linux-aspeed+subscribe-nomail@lists.ozlabs.org>", "List-Unsubscribe": "<mailto:linux-aspeed+unsubscribe@lists.ozlabs.org>", "Precedence": "list", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-ID": "<20260414-upstream_pinctrl-v6-2-709f2127da33@aspeedtech.com>", "References": "<20260414-upstream_pinctrl-v6-0-709f2127da33@aspeedtech.com>", "In-Reply-To": "<20260414-upstream_pinctrl-v6-0-709f2127da33@aspeedtech.com>", "To": "Lee Jones <lee@kernel.org>, Rob Herring <robh@kernel.org>, \"Krzysztof\n Kozlowski\" <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, \"Joel\n Stanley\" <joel@jms.id.au>, Andrew Jeffery <andrew@codeconstruct.com.au>,\n\t\"Linus Walleij\" <linusw@kernel.org>, Billy Tsai <billy_tsai@aspeedtech.com>,\n\t\"Bartosz Golaszewski\" <brgl@kernel.org>, Ryan Chen <ryan_chen@aspeedtech.com>", "CC": "Andrew Jeffery <andrew@aj.id.au>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>, <linux-aspeed@lists.ozlabs.org>,\n\t<linux-kernel@vger.kernel.org>, <openbmc@lists.ozlabs.org>,\n\t<linux-gpio@vger.kernel.org>, <linux-clk@vger.kernel.org>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1776159555; l=5282;\n i=billy_tsai@aspeedtech.com; s=20251118; h=from:subject:message-id;\n bh=1adOzN89BJlq56ikXHBSEpPPcUIuo6AxNQzlti780x8=;\n b=lUxsJPh0Uh7M+PWU69Q6zBK9UxsmwYd4K1lc21YcI0lMbJ4NkQEgtwxkFdHUSNqAGs5WfsgrS\n cSLI5mQe7UKDgA0/J7hhHmfYWatKrdD5vEoGuNo2FRqVHBV0VH/Bgfb", "X-Developer-Key": "i=billy_tsai@aspeedtech.com; a=ed25519;\n pk=/A8qvgZ6CPfnwKgT6/+k+nvXOkN477MshEGJvVdzeeQ=", "X-Spam-Status": "No, score=0.0 required=5.0 tests=SPF_HELO_FAIL,SPF_PASS\n\tautolearn=disabled version=4.0.1", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "AST2700 consists of two interconnected SoC instances, each with its own\nSystem Control Unit (SCU). The SCU0 provides pin control, interrupt\ncontrollers, clocks, resets, and address-space mappings for the\nSecondary and Tertiary Service Processors (SSP and TSP).\n\nDescribe the SSP/TSP address mappings using the standard\nmemory-region and memory-region-names properties.\n\nDisallow legacy child nodes that are not present on AST2700, including\np2a-control and smp-memram. The latter is unnecessary as software can\naccess the scratch registers via the SCU syscon.\n\nAlso allow the AST2700 SoC0 pin controller to be described as a child\nnode of the SCU0, and add an example illustrating the SCU0 layout,\nincluding reserved-memory, interrupt controllers, and pinctrl.\n\nSigned-off-by: Billy Tsai <billy_tsai@aspeedtech.com>\n---\n .../bindings/mfd/aspeed,ast2x00-scu.yaml | 112 +++++++++++++++++++++\n 1 file changed, 112 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml\nindex a87f31fce019..d65897576a40 100644\n--- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml\n+++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml\n@@ -46,6 +46,17 @@ properties:\n '#reset-cells':\n const: 1\n \n+ memory-region:\n+ items:\n+ - description: Region mapped through the first SSP address window.\n+ - description: Region mapped through the second SSP address window.\n+ - description: Region mapped through the TSP address window.\n+ memory-region-names:\n+ items:\n+ - const: ssp-0\n+ - const: ssp-1\n+ - const: tsp\n+\n patternProperties:\n '^p2a-control@[0-9a-f]+$':\n description: >\n@@ -87,6 +98,7 @@ patternProperties:\n - aspeed,ast2400-pinctrl\n - aspeed,ast2500-pinctrl\n - aspeed,ast2600-pinctrl\n+ - aspeed,ast2700-soc0-pinctrl\n \n required:\n - compatible\n@@ -156,6 +168,29 @@ required:\n - '#clock-cells'\n - '#reset-cells'\n \n+allOf:\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ anyOf:\n+ - const: aspeed,ast2700-scu0\n+ - const: aspeed,ast2700-scu1\n+ then:\n+ patternProperties:\n+ '^p2a-control@[0-9a-f]+$': false\n+ '^smp-memram@[0-9a-f]+$': false\n+\n+ - if:\n+ properties:\n+ compatible:\n+ contains:\n+ const: aspeed,ast2700-scu0\n+ else:\n+ properties:\n+ memory-region: false\n+ memory-region-names: false\n+\n additionalProperties: false\n \n examples:\n@@ -180,4 +215,81 @@ examples:\n reg = <0x7c 0x4>, <0x150 0x8>;\n };\n };\n+\n+ - |\n+ / {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ reserved-memory {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+ ranges;\n+\n+ ssp_region_0: memory@400000000 {\n+ reg = <0x4 0x00000000 0x0 0x01000000>;\n+ no-map;\n+ };\n+\n+ ssp_region_1: memory@401000000 {\n+ reg = <0x4 0x01000000 0x0 0x01000000>;\n+ no-map;\n+ };\n+\n+ tsp_region: memory@402000000 {\n+ reg = <0x4 0x02000000 0x0 0x01000000>;\n+ no-map;\n+ };\n+ };\n+\n+ bus {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ syscon@12c02000 {\n+ compatible = \"aspeed,ast2700-scu0\", \"syscon\", \"simple-mfd\";\n+ reg = <0 0x12c02000 0 0x1000>;\n+ ranges = <0x0 0x0 0x12c02000 0x1000>;\n+ #address-cells = <1>;\n+ #size-cells = <1>;\n+ #clock-cells = <1>;\n+ #reset-cells = <1>;\n+\n+ memory-region = <&ssp_region_0>, <&ssp_region_1>,\n+ <&tsp_region>;\n+ memory-region-names = \"ssp-0\", \"ssp-1\", \"tsp\";\n+\n+ silicon-id@0 {\n+ compatible = \"aspeed,ast2700-silicon-id\", \"aspeed,silicon-id\";\n+ reg = <0x0 0x4>;\n+ };\n+\n+ interrupt-controller@1b0 {\n+ compatible = \"aspeed,ast2700-scu-ic0\";\n+ reg = <0x1b0 0x4>;\n+ #interrupt-cells = <1>;\n+ interrupts-extended = <&intc0 97>;\n+ interrupt-controller;\n+ };\n+\n+ interrupt-controller@1e0 {\n+ compatible = \"aspeed,ast2700-scu-ic1\";\n+ reg = <0x1e0 0x4>;\n+ #interrupt-cells = <1>;\n+ interrupts-extended = <&intc0 98>;\n+ interrupt-controller;\n+ };\n+\n+ pinctrl@400 {\n+ compatible = \"aspeed,ast2700-soc0-pinctrl\";\n+ reg = <0x400 0x318>;\n+ emmc-state {\n+ function = \"EMMC\";\n+ groups = \"EMMCG1\";\n+ };\n+ };\n+ };\n+ };\n+ };\n+\n ...\n", "prefixes": [ "v6", "2/3" ] }