Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.0/patches/2221288/?format=api
{ "id": 2221288, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2221288/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260409-fix-unit-address-v1-5-946840930af2@iscas.ac.cn>", "date": "2026-04-09T06:40:15", "name": "[5/5] hw/riscv: Use hex unit addresses in FDT CPU nodes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "208771c1a9cb62bfa8d351a1415b3ac8e36286d5", "submitter": { "id": 91053, "url": "http://patchwork.ozlabs.org/api/1.0/people/91053/?format=api", "name": "Vivian Wang", "email": "wangruikang@iscas.ac.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409-fix-unit-address-v1-5-946840930af2@iscas.ac.cn/mbox/", "series": [ { "id": 499239, "url": "http://patchwork.ozlabs.org/api/1.0/series/499239/?format=api", "date": "2026-04-09T06:40:10", "name": "hw: Fix unit addresses of FDT CPU nodes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499239/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221288/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frr1w58Vhz1yJK\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 09 Apr 2026 16:41:38 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wAj4U-0007te-Us; Thu, 09 Apr 2026 02:40:58 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <wangruikang@iscas.ac.cn>)\n id 1wAj4N-0007qz-QV; Thu, 09 Apr 2026 02:40:52 -0400", "from smtp81.cstnet.cn ([159.226.251.81] helo=cstnet.cn)\n by eggs.gnu.org with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA1:256)\n (Exim 4.90_1) (envelope-from <wangruikang@iscas.ac.cn>)\n id 1wAj4H-0004PW-Du; Thu, 09 Apr 2026 02:40:50 -0400", "from [127.0.0.2] (unknown [36.110.52.2])\n by APP-03 (Coremail) with SMTP id rQCowABnht3aSddpeI91DQ--.34096S7;\n Thu, 09 Apr 2026 14:40:27 +0800 (CST)" ], "From": "Vivian Wang <wangruikang@iscas.ac.cn>", "Date": "Thu, 09 Apr 2026 14:40:15 +0800", "Subject": "[PATCH 5/5] hw/riscv: Use hex unit addresses in FDT CPU nodes", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260409-fix-unit-address-v1-5-946840930af2@iscas.ac.cn>", "References": "<20260409-fix-unit-address-v1-0-946840930af2@iscas.ac.cn>", "In-Reply-To": "<20260409-fix-unit-address-v1-0-946840930af2@iscas.ac.cn>", "To": "qemu-devel@nongnu.org", "Cc": "Peter Maydell <peter.maydell@linaro.org>,\n Leif Lindholm <leif.lindholm@oss.qualcomm.com>, qemu-arm@nongnu.org,\n Song Gao <gaosong@loongson.cn>, Bibo Mao <maobibo@loongson.cn>,\n Jiaxun Yang <jiaxun.yang@flygoat.com>, Paul Burton <paulburton@kernel.org>,\n Aleksandar Rikalo <arikalo@gmail.com>, =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?q?=C3=A9?= <philmd@linaro.org>, Jia Liu <proljc@gmail.com>,\n Stafford Horne <shorne@gmail.com>,\n Alistair Francis <Alistair.Francis@wdc.com>,\n Palmer Dabbelt <palmer@dabbelt.com>, Weiwei Li <liwei1518@gmail.com>,\n Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>,\n Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,\n Chao Liu <chao.liu.zevorn@gmail.com>, qemu-riscv@nongnu.org,\n Vivian Wang <wangruikang@iscas.ac.cn>", "X-Mailer": "b4 0.15.1", "X-CM-TRANSID": "rQCowABnht3aSddpeI91DQ--.34096S7", "X-Coremail-Antispam": "1UD129KBjvJXoWxuryrZF1fWw15Zr1UCw48WFg_yoW5uw1rpF\n WkKFnIv348tF43WaySya4jyr1a9rnxW347K397C397Jr45ury5XFn2ya40yryDKa4kXa15\n ZFZ5WryYq3Zavr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDU0xBIdaVrnRJUUUmq14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0\n rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI\n kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2\n z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F\n 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE\n 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I\n x0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkEbVWUJVW8\n JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2\n ka0xkIwI1lc7CjxVAaw2AFwI0_GFv_Wryl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Y\n z7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zV\n AF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1l\n IxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r\n 1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIY\n CTnIWIevJa73UjIFyTuYvjTRZfHUDUUUU", "X-Originating-IP": "[36.110.52.2]", "X-CM-SenderInfo": "pzdqw2pxlnt03j6l2u1dvotugofq/", "Received-SPF": "pass client-ip=159.226.251.81;\n envelope-from=wangruikang@iscas.ac.cn; helo=cstnet.cn", "X-Spam_score_int": "-41", "X-Spam_score": "-4.2", "X-Spam_bar": "----", "X-Spam_report": "(-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "These unit addresses should have been in hex, not decimal, as per de\nfacto convention [1]. Fix them.\n\nLink: https://lore.kernel.org/devicetree-spec/CAL_JsqJFv3+UJ-bjLGk0i7Wc+spsowCrqQZ_s3P4gN8r1W-Q-w@mail.gmail.com/ # [1]\nSigned-off-by: Vivian Wang <wangruikang@iscas.ac.cn>\n---\n hw/riscv/sifive_u.c | 9 +++++----\n hw/riscv/spike.c | 4 ++--\n hw/riscv/virt.c | 4 ++--\n 3 files changed, 9 insertions(+), 8 deletions(-)", "diff": "diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c\nindex 7ec67b2565..54f3bcc3b2 100644\n--- a/hw/riscv/sifive_u.c\n+++ b/hw/riscv/sifive_u.c\n@@ -168,8 +168,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,\n \n for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {\n int cpu_phandle = phandle++;\n- nodename = g_strdup_printf(\"/cpus/cpu@%d\", cpu);\n- char *intc = g_strdup_printf(\"/cpus/cpu@%d/interrupt-controller\", cpu);\n+ nodename = g_strdup_printf(\"/cpus/cpu@%x\", (unsigned)cpu);\n+ char *intc = g_strdup_printf(\"/cpus/cpu@%x/interrupt-controller\",\n+ (unsigned)cpu);\n qemu_fdt_add_subnode(fdt, nodename);\n /* cpu 0 is the management hart that does not have mmu */\n if (cpu != 0) {\n@@ -198,7 +199,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,\n cells = g_new0(uint32_t, ms->smp.cpus * 4);\n for (cpu = 0; cpu < ms->smp.cpus; cpu++) {\n nodename =\n- g_strdup_printf(\"/cpus/cpu@%d/interrupt-controller\", cpu);\n+ g_strdup_printf(\"/cpus/cpu@%x/interrupt-controller\", (unsigned)cpu);\n uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);\n cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);\n cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);\n@@ -249,7 +250,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,\n cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2);\n for (cpu = 0; cpu < ms->smp.cpus; cpu++) {\n nodename =\n- g_strdup_printf(\"/cpus/cpu@%d/interrupt-controller\", cpu);\n+ g_strdup_printf(\"/cpus/cpu@%x/interrupt-controller\", (unsigned)cpu);\n uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);\n /* cpu 0 is the management hart that does not have S-mode */\n if (cpu == 0) {\ndiff --git a/hw/riscv/spike.c b/hw/riscv/spike.c\nindex 35c696f891..cac01ea1ff 100644\n--- a/hw/riscv/spike.c\n+++ b/hw/riscv/spike.c\n@@ -105,8 +105,8 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap,\n for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {\n cpu_phandle = phandle++;\n \n- cpu_name = g_strdup_printf(\"/cpus/cpu@%d\",\n- s->soc[socket].hartid_base + cpu);\n+ cpu_name = g_strdup_printf(\"/cpus/cpu@%\" PRIx32,\n+ s->soc[socket].hartid_base + (uint32_t)cpu);\n qemu_fdt_add_subnode(fdt, cpu_name);\n if (is_32_bit) {\n qemu_fdt_setprop_string(fdt, cpu_name, \"mmu-type\", \"riscv,sv32\");\ndiff --git a/hw/riscv/virt.c b/hw/riscv/virt.c\nindex a1c323e66d..42a83dd829 100644\n--- a/hw/riscv/virt.c\n+++ b/hw/riscv/virt.c\n@@ -248,8 +248,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,\n \n cpu_phandle = (*phandle)++;\n \n- cpu_name = g_strdup_printf(\"/cpus/cpu@%d\",\n- s->soc[socket].hartid_base + cpu);\n+ cpu_name = g_strdup_printf(\"/cpus/cpu@%\" PRIx32,\n+ s->soc[socket].hartid_base + (uint32_t)cpu);\n qemu_fdt_add_subnode(ms->fdt, cpu_name);\n \n if (satp_mode_max != -1) {\n", "prefixes": [ "5/5" ] }