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GET /api/1.0/patches/2221272/?format=api
{ "id": 2221272, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2221272/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260409035015.132370-5-richard.henderson@linaro.org>", "date": "2026-04-09T03:50:12", "name": "[v2,4/7] target/arm: Store SVC immediate for user-only", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c1480b29956b63652cb2e52f59f5325db94a9287", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.0/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409035015.132370-5-richard.henderson@linaro.org/mbox/", "series": [ { "id": 499232, "url": "http://patchwork.ozlabs.org/api/1.0/series/499232/?format=api", "date": "2026-04-09T03:50:08", "name": "target/arm: Remove bswap_code", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499232/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221272/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Qe2DRoaT;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frmGF6ZFwz1yD3\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 09 Apr 2026 13:52:05 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wAgPf-0000fX-Hk; Wed, 08 Apr 2026 23:50:39 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wAgPe-0000f7-Cz\n for qemu-devel@nongnu.org; Wed, 08 Apr 2026 23:50:38 -0400", "from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wAgPc-0003t1-Uu\n for qemu-devel@nongnu.org; Wed, 08 Apr 2026 23:50:38 -0400", "by mail-pl1-x634.google.com with SMTP id\n d9443c01a7336-2ab232cc803so2604975ad.3\n for <qemu-devel@nongnu.org>; Wed, 08 Apr 2026 20:50:36 -0700 (PDT)", "from stoup.. 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helo=mail-pl1-x634.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Rather than re-reading the insn during syscall processing to\nfind the immediate, store it in CPUARMState during translate.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu.h | 1 +\n linux-user/arm/cpu_loop.c | 13 ++++---------\n target/arm/tcg/translate.c | 19 +++++++++++++++++--\n 3 files changed, 22 insertions(+), 11 deletions(-)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex b11a31c807..5b564c7113 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -817,6 +817,7 @@ typedef struct CPUArchState {\n bool tagged_addr_enable;\n #else\n /* For usermode syscall translation. */\n+ uint32_t syscall_info;\n bool eabi;\n #endif /* !CONFIG_USER_ONLY */\n } CPUARMState;\ndiff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c\nindex 19874f4c72..86f13ad83a 100644\n--- a/linux-user/arm/cpu_loop.c\n+++ b/linux-user/arm/cpu_loop.c\n@@ -271,7 +271,6 @@ void cpu_loop(CPUARMState *env)\n {\n CPUState *cs = env_cpu(env);\n int trapnr, si_signo, si_code;\n- unsigned int n, insn;\n abi_ulong ret;\n \n for(;;) {\n@@ -312,20 +311,16 @@ void cpu_loop(CPUARMState *env)\n break;\n case EXCP_SWI:\n {\n+ unsigned int n;\n+\n env->eabi = true;\n /* system call */\n if (env->thumb) {\n /* Thumb is always EABI style with syscall number in r7 */\n n = env->regs[7];\n } else {\n- /*\n- * Equivalent of kernel CONFIG_OABI_COMPAT: read the\n- * Arm SVC insn to extract the immediate, which is the\n- * syscall number in OABI.\n- */\n- /* FIXME - what to do if get_user() fails? */\n- get_user_code_u32(insn, env->regs[15] - 4, env);\n- n = insn & 0xffffff;\n+ /* The 24-bit SVC immediate is stored during translate. */\n+ n = env->syscall_info;\n if (n == 0) {\n /* zero immediate: EABI, syscall number in r7 */\n n = env->regs[7];\ndiff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex ce427c5a3c..ec21e33a06 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -1158,6 +1158,21 @@ void unallocated_encoding(DisasContext *s)\n gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized());\n }\n \n+static void gen_exception_swi(DisasContext *s)\n+{\n+#ifdef CONFIG_USER_ONLY\n+# ifndef TARGET_AARCH64\n+ /*\n+ * Only 16-bits of the immediate are recorded in the syndrome,\n+ * so store the entire 24-bit immediate for cpu_loop().\n+ */\n+ tcg_gen_st_i32(tcg_constant_i32(s->svc_imm), tcg_env,\n+ offsetof(CPUARMState, syscall_info));\n+# endif\n+#endif\n+ gen_exception(EXCP_SWI, syn_aa32_svc(s->svc_imm, s->thumb));\n+}\n+\n /* Force a TB lookup after an instruction that changes the CPU state. */\n void gen_lookup_tb(DisasContext *s)\n {\n@@ -6781,7 +6796,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n switch (dc->base.is_jmp) {\n case DISAS_SWI:\n gen_ss_advance(dc);\n- gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));\n+ gen_exception_swi(dc);\n break;\n case DISAS_HVC:\n gen_ss_advance(dc);\n@@ -6854,7 +6869,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n gen_helper_yield(tcg_env);\n break;\n case DISAS_SWI:\n- gen_exception(EXCP_SWI, syn_aa32_svc(dc->svc_imm, dc->thumb));\n+ gen_exception_swi(dc);\n break;\n case DISAS_HVC:\n gen_exception_el(EXCP_HVC, syn_aa32_hvc(dc->svc_imm), 2);\n", "prefixes": [ "v2", "4/7" ] }