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GET /api/1.0/patches/2221268/?format=api
{ "id": 2221268, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2221268/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260409035015.132370-7-richard.henderson@linaro.org>", "date": "2026-04-09T03:50:14", "name": "[v2,6/7] target/arm: Introduce EXCP_NWFPE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4a79c7b2a7eb9333d4a0ce67672860bc62a05673", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.0/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260409035015.132370-7-richard.henderson@linaro.org/mbox/", "series": [ { "id": 499232, "url": "http://patchwork.ozlabs.org/api/1.0/series/499232/?format=api", "date": "2026-04-09T03:50:08", "name": "target/arm: Remove bswap_code", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499232/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221268/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ZPPqX3Mb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frmFV5LvWz1yD3\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 09 Apr 2026 13:51:26 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wAgPm-0000ib-Hw; Wed, 08 Apr 2026 23:50:46 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wAgPl-0000hm-48\n for qemu-devel@nongnu.org; Wed, 08 Apr 2026 23:50:45 -0400", "from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wAgPj-0003tf-FK\n for qemu-devel@nongnu.org; Wed, 08 Apr 2026 23:50:44 -0400", "by mail-pl1-x62a.google.com with SMTP id\n d9443c01a7336-2ad21f437eeso2111585ad.0\n for <qemu-devel@nongnu.org>; Wed, 08 Apr 2026 20:50:43 -0700 (PDT)", "from stoup.. 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helo=mail-pl1-x62a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "We don't normally emulate any coprocessor {1,2} insns, but\nlinux-user would like to emulate these fpa11 insns.\n\nFilter these, raise a special exception, and store the\ninstruction in CPUARMState.syscall_info rather than reload\nthe instruction in the linux-user cpu_loop.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/cpu.h | 1 +\n linux-user/arm/cpu_loop.c | 34 ++++++----------------------------\n target/arm/tcg/translate.c | 27 +++++++++++++++++++++++++++\n 3 files changed, 34 insertions(+), 28 deletions(-)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 5b564c7113..8f1afca2ae 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -64,6 +64,7 @@\n #define EXCP_VINMI 27\n #define EXCP_VFNMI 28\n #define EXCP_MON_TRAP 29 /* AArch32 trap to Monitor mode */\n+#define EXCP_NWFPE 30 /* linux-user fpa11 emulation */\n /* NB: add new EXCP_ defines to the array in arm_log_exception() too */\n \n #define ARMV7M_EXCP_RESET 1\ndiff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c\nindex 4f7c5dab9c..ae941ba9af 100644\n--- a/linux-user/arm/cpu_loop.c\n+++ b/linux-user/arm/cpu_loop.c\n@@ -29,19 +29,6 @@\n #include \"user/page-protection.h\"\n #include \"target/arm/syndrome.h\"\n \n-#define get_user_code_u32(x, gaddr, env) \\\n- ({ abi_long __r = get_user_u32((x), (gaddr)); \\\n- if (!__r && bswap_code(arm_sctlr_b(env))) { \\\n- (x) = bswap32(x); \\\n- } \\\n- __r; \\\n- })\n-\n-/*\n- * Note that if we need to do data accesses here, they should do a\n- * bswap if arm_cpu_bswap_data() returns true.\n- */\n-\n /*\n * Similar to code in accel/tcg/user-exec.c, but outside the execution loop.\n * Must be called with mmap_lock.\n@@ -262,24 +249,15 @@ void cpu_loop(CPUARMState *env)\n qemu_process_cpu_events(cs);\n \n switch(trapnr) {\n+ case EXCP_NWFPE:\n+ if (emulate_arm_fpa11(env, env->syscall_info)) {\n+ break;\n+ }\n+ /* fall through */\n case EXCP_UDEF:\n case EXCP_NOCP:\n case EXCP_INVSTATE:\n- {\n- uint32_t opcode;\n-\n- /* we handle the FPU emulation here, as Linux */\n- /* we get the opcode */\n- /* FIXME - what to do if get_user() fails? */\n- get_user_code_u32(opcode, env->regs[15], env);\n-\n- if (!env->thumb && emulate_arm_fpa11(env, opcode)) {\n- break;\n- }\n-\n- force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN,\n- env->regs[15]);\n- }\n+ force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->regs[15]);\n break;\n case EXCP_SWI:\n {\ndiff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c\nindex 0447be0907..d910a007db 100644\n--- a/target/arm/tcg/translate.c\n+++ b/target/arm/tcg/translate.c\n@@ -2358,8 +2358,26 @@ static bool valid_cp(DisasContext *s, int cp)\n return cp < 8 || cp >= 14;\n }\n \n+static bool maybe_nwfpe(DisasContext *s, int cp)\n+{\n+#ifdef CONFIG_USER_ONLY\n+# if defined(CONFIG_LINUX) && !defined(TARGET_AARCH64)\n+ if (!s->thumb && (cp == 1 || cp == 2)) {\n+ tcg_gen_st_i32(tcg_constant_i32(s->insn), tcg_env,\n+ offsetof(CPUARMState, syscall_info));\n+ gen_exception_insn(s, 0, EXCP_NWFPE, syn_uncategorized());\n+ return true;\n+ }\n+# endif\n+#endif\n+ return false;\n+}\n+\n static bool trans_MCR(DisasContext *s, arg_MCR *a)\n {\n+ if (maybe_nwfpe(s, a->cp)) {\n+ return true;\n+ }\n if (!valid_cp(s, a->cp)) {\n return false;\n }\n@@ -2370,6 +2388,9 @@ static bool trans_MCR(DisasContext *s, arg_MCR *a)\n \n static bool trans_MRC(DisasContext *s, arg_MRC *a)\n {\n+ if (maybe_nwfpe(s, a->cp)) {\n+ return true;\n+ }\n if (!valid_cp(s, a->cp)) {\n return false;\n }\n@@ -2380,6 +2401,9 @@ static bool trans_MRC(DisasContext *s, arg_MRC *a)\n \n static bool trans_MCRR(DisasContext *s, arg_MCRR *a)\n {\n+ if (maybe_nwfpe(s, a->cp)) {\n+ return true;\n+ }\n if (!valid_cp(s, a->cp)) {\n return false;\n }\n@@ -2390,6 +2414,9 @@ static bool trans_MCRR(DisasContext *s, arg_MCRR *a)\n \n static bool trans_MRRC(DisasContext *s, arg_MRRC *a)\n {\n+ if (maybe_nwfpe(s, a->cp)) {\n+ return true;\n+ }\n if (!valid_cp(s, a->cp)) {\n return false;\n }\n", "prefixes": [ "v2", "6/7" ] }