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GET /api/1.0/patches/2221212/?format=api
{ "id": 2221212, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2221212/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260408041953.1899532-11-brian.cain@oss.qualcomm.com>", "date": "2026-04-08T04:19:35", "name": "[v4,10/28] target/hexagon: Implement exec_interrupt, set_irq", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ba8f71d4d680b4e7004c131851a132954d1a5ec4", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/1.0/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408041953.1899532-11-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 499179, "url": "http://patchwork.ozlabs.org/api/1.0/series/499179/?format=api", "date": "2026-04-08T04:19:31", "name": "Hexagon system emulation - Part 2/3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499179/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221212/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=idi3LCho;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=BGj8W1pn;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/cpu.c | 84 ++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 84 insertions(+)", "diff": "diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 0670225d858..a23cc475a98 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -16,6 +16,7 @@\n */\n \n #include \"qemu/osdep.h\"\n+#include \"qemu/log.h\"\n #include \"qemu/qemu-print.h\"\n #include \"cpu.h\"\n #include \"internal.h\"\n@@ -31,10 +32,12 @@\n #include \"hex_mmu.h\"\n \n #ifndef CONFIG_USER_ONLY\n+#include \"macros.h\"\n #include \"sys_macros.h\"\n #include \"accel/tcg/cpu-ldst.h\"\n #include \"qemu/main-loop.h\"\n #include \"hex_interrupts.h\"\n+#include \"exec/cpu-interrupt.h\"\n #endif\n \n static void hexagon_v66_cpu_init(Object *obj) { }\n@@ -309,6 +312,36 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs,\n cpu_env(cs)->gpr[HEX_REG_PC] = tb->pc;\n }\n \n+#ifndef CONFIG_USER_ONLY\n+bool hexagon_thread_is_enabled(CPUHexagonState *env)\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t modectl;\n+ uint32_t thread_enabled_mask;\n+ bool E_bit;\n+\n+ if (!cpu->globalregs) {\n+ return true;\n+ }\n+ modectl =\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_MODECTL,\n+ env->threadId);\n+ thread_enabled_mask = GET_FIELD(MODECTL_E, modectl);\n+ E_bit = thread_enabled_mask & (0x1 << env->threadId);\n+\n+ return E_bit;\n+}\n+\n+static bool hexagon_cpu_has_work(CPUState *cs)\n+{\n+ CPUHexagonState *env = cpu_env(cs);\n+\n+ return hexagon_thread_is_enabled(env) &&\n+ (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI\n+ | CPU_INTERRUPT_K0_UNLOCK | CPU_INTERRUPT_TLB_UNLOCK));\n+}\n+#endif\n+\n static void hexagon_restore_state_to_opc(CPUState *cs,\n const TranslationBlock *tb,\n const uint64_t *data)\n@@ -408,10 +441,58 @@ static int hexagon_cpu_mmu_index(CPUState *cs, bool ifetch)\n return MMU_USER_IDX;\n }\n \n+#if !defined(CONFIG_USER_ONLY)\n+static void hexagon_cpu_set_irq(void *opaque, int irq, int level)\n+{\n+ HexagonCPU *cpu = HEXAGON_CPU(opaque);\n+ CPUState *cs = CPU(cpu);\n+ CPUHexagonState *env = cpu_env(cs);\n+\n+ switch (irq) {\n+ case HEXAGON_CPU_IRQ_0 ... HEXAGON_CPU_IRQ_7:\n+ qemu_log_mask(CPU_LOG_INT, \"%s: irq %d, level %d\\n\",\n+ __func__, irq, level);\n+ if (level) {\n+ hex_raise_interrupts(env, 1 << irq, CPU_INTERRUPT_HARD);\n+ }\n+ break;\n+ default:\n+ g_assert_not_reached();\n+ }\n+}\n+#endif\n+\n static void hexagon_cpu_init(Object *obj)\n {\n+#if !defined(CONFIG_USER_ONLY)\n+ HexagonCPU *cpu = HEXAGON_CPU(obj);\n+ qdev_init_gpio_in(DEVICE(cpu), hexagon_cpu_set_irq, 8);\n+#endif\n }\n \n+#ifndef CONFIG_USER_ONLY\n+\n+static bool hexagon_cpu_exec_interrupt(CPUState *cs, int interrupt_request)\n+{\n+ CPUHexagonState *env = cpu_env(cs);\n+ if (interrupt_request & CPU_INTERRUPT_TLB_UNLOCK) {\n+ cs->halted = false;\n+ cpu_reset_interrupt(cs, CPU_INTERRUPT_TLB_UNLOCK);\n+ return true;\n+ }\n+ if (interrupt_request & CPU_INTERRUPT_K0_UNLOCK) {\n+ cs->halted = false;\n+ cpu_reset_interrupt(cs, CPU_INTERRUPT_K0_UNLOCK);\n+ return true;\n+ }\n+ if (interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI)) {\n+ return hex_check_interrupts(env);\n+ }\n+ return false;\n+}\n+\n+#endif\n+\n static const TCGCPUOps hexagon_tcg_ops = {\n /* MTTCG not yet supported: require strict ordering */\n .guest_default_memory_order = TCG_MO_ALL,\n@@ -422,6 +503,9 @@ static const TCGCPUOps hexagon_tcg_ops = {\n .synchronize_from_tb = hexagon_cpu_synchronize_from_tb,\n .restore_state_to_opc = hexagon_restore_state_to_opc,\n .mmu_index = hexagon_cpu_mmu_index,\n+#if !defined(CONFIG_USER_ONLY)\n+ .cpu_exec_interrupt = hexagon_cpu_exec_interrupt,\n+#endif /* !CONFIG_USER_ONLY */\n };\n \n static void hexagon_cpu_class_init(ObjectClass *c, const void *data)\n", "prefixes": [ "v4", "10/28" ] }