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GET /api/1.0/patches/2221198/?format=api
{ "id": 2221198, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2221198/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<e66f33dc979f03215ab0c0738a14b96e8f8a30cd.1775665981.git.matheus.bernardino@oss.qualcomm.com>", "date": "2026-04-08T16:37:03", "name": "[v3,12/16] tests/hexagon: add tests for v68 HVX IEEE float arithmetics", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f9d537d01cb3e65bc5915ef96fe2e28b27d69c08", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/1.0/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "delegate": null, "mbox": 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4LYoKXvv2UFZzUgWqdkvV6thEaJbpFRQHlXeaSS/BwctX0c/h7I/wVp44iMo/oK6Eaqm8FdIjEz\n Z73oJyyp8ykSFMXYZFkm1fn83NPYT36NAdZNVkEQ1DoyBkBF3jgXDlR5bQ7LN9pqX+GmLAtUcC7\n rxrQB1kriR", "X-Received": [ "by 2002:a05:7022:7a4:b0:127:33e0:ea40 with SMTP id\n a92af1059eb24-12c28bf1e52mr87633c88.15.1775666242576;\n Wed, 08 Apr 2026 09:37:22 -0700 (PDT)", "by 2002:a05:7022:7a4:b0:127:33e0:ea40 with SMTP id\n a92af1059eb24-12c28bf1e52mr87612c88.15.1775666241818;\n Wed, 08 Apr 2026 09:37:21 -0700 (PDT)" ], "From": "Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>", "To": "qemu-devel@nongnu.org", "Cc": "richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com", "Subject": "[PATCH v3 12/16] tests/hexagon: add tests for v68 HVX IEEE float\n arithmetics", "Date": "Wed, 8 Apr 2026 09:37:03 -0700", "Message-Id": "\n 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envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0b-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\n---\n tests/tcg/hexagon/hex_test.h | 4 +\n tests/tcg/hexagon/hvx_misc.h | 41 ++++++++\n tests/tcg/hexagon/fp_hvx.c | 155 ++++++++++++++++++++++++++++\n tests/tcg/hexagon/fp_hvx_disabled.c | 57 ++++++++++\n tests/tcg/hexagon/Makefile.target | 8 ++\n 5 files changed, 265 insertions(+)\n create mode 100644 tests/tcg/hexagon/fp_hvx.c\n create mode 100644 tests/tcg/hexagon/fp_hvx_disabled.c", "diff": "diff --git a/tests/tcg/hexagon/hex_test.h b/tests/tcg/hexagon/hex_test.h\nindex cfed06a58b..e7a6644d41 100644\n--- a/tests/tcg/hexagon/hex_test.h\n+++ b/tests/tcg/hexagon/hex_test.h\n@@ -19,6 +19,8 @@\n #ifndef HEX_TEST_H\n #define HEX_TEST_H\n \n+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))\n+\n static inline void __check32(int line, uint32_t val, uint32_t expect)\n {\n if (val != expect) {\n@@ -110,6 +112,7 @@ static inline void __check64_ne(int line, uint64_t val, uint64_t expect)\n \n /* Some useful floating point values */\n const uint32_t SF_INF = 0x7f800000;\n+const uint32_t SF_INF_neg = 0xff800000;\n const uint32_t SF_QNaN = 0x7fc00000;\n const uint32_t SF_QNaN_special = 0x7f800001;\n const uint32_t SF_SNaN = 0x7fb00000;\n@@ -128,6 +131,7 @@ const uint32_t SF_large_pos = 0x5afa572e;\n const uint32_t SF_any = 0x3f800000;\n const uint32_t SF_denorm = 0x00000001;\n const uint32_t SF_random = 0x346001d6;\n+const uint32_t SF_neg_two = 0xc0000000;\n \n const uint64_t DF_QNaN = 0x7ff8000000000000ULL;\n const uint64_t DF_SNaN = 0x7ff7000000000000ULL;\ndiff --git a/tests/tcg/hexagon/hvx_misc.h b/tests/tcg/hexagon/hvx_misc.h\nindex 2e868340fd..0330cb289d 100644\n--- a/tests/tcg/hexagon/hvx_misc.h\n+++ b/tests/tcg/hexagon/hvx_misc.h\n@@ -18,6 +18,8 @@\n #ifndef HVX_MISC_H\n #define HVX_MISC_H\n \n+#include \"hex_test.h\"\n+\n static inline void check(int line, int i, int j,\n uint64_t result, uint64_t expect)\n {\n@@ -34,8 +36,10 @@ typedef union {\n uint64_t ud[MAX_VEC_SIZE_BYTES / 8];\n int64_t d[MAX_VEC_SIZE_BYTES / 8];\n uint32_t uw[MAX_VEC_SIZE_BYTES / 4];\n+ uint32_t sf[MAX_VEC_SIZE_BYTES / 4]; /* convenience alias */\n int32_t w[MAX_VEC_SIZE_BYTES / 4];\n uint16_t uh[MAX_VEC_SIZE_BYTES / 2];\n+ uint16_t hf[MAX_VEC_SIZE_BYTES / 2]; /* convenience alias */\n int16_t h[MAX_VEC_SIZE_BYTES / 2];\n uint8_t ub[MAX_VEC_SIZE_BYTES / 1];\n int8_t b[MAX_VEC_SIZE_BYTES / 1];\n@@ -63,7 +67,9 @@ static inline void check_output_##FIELD(int line, size_t num_vectors) \\\n \n CHECK_OUTPUT_FUNC(d, 8)\n CHECK_OUTPUT_FUNC(w, 4)\n+CHECK_OUTPUT_FUNC(sf, 4)\n CHECK_OUTPUT_FUNC(h, 2)\n+CHECK_OUTPUT_FUNC(hf, 2)\n CHECK_OUTPUT_FUNC(b, 1)\n \n static inline void init_buffers(void)\n@@ -81,6 +87,33 @@ static inline void init_buffers(void)\n }\n }\n \n+static const uint32_t FP_VALUES[] = {\n+ SF_INF, SF_INF_neg, SF_QNaN, SF_QNaN_special, SF_SNaN, SF_QNaN_neg,\n+ SF_SNaN_neg, SF_HEX_NaN, SF_zero, SF_zero_neg, SF_one, SF_one_recip,\n+ SF_one_invsqrta, SF_two, SF_four, SF_small_neg, SF_large_pos, SF_any,\n+ SF_denorm, SF_random, SF_neg_two,\n+};\n+#define FP_VALUES_MAX ARRAY_SIZE(FP_VALUES)\n+\n+static inline void init_buffers_fp(void)\n+{\n+ _Static_assert(BUFSIZE * (MAX_VEC_SIZE_BYTES / 4) >\n+ FP_VALUES_MAX * FP_VALUES_MAX,\n+ \"test arrays can't fit all FP_VALUES combinations\");\n+ int counter1 = 0, counter2 = 0;\n+ for (int i = 0; i < BUFSIZE; i++) {\n+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {\n+ buffer0[i].sf[j] = FP_VALUES[counter1];\n+ buffer1[i].sf[j] = FP_VALUES[counter2];\n+ counter2++;\n+ if (counter2 == FP_VALUES_MAX) {\n+ counter2 = 0;\n+ counter1 = (counter1 + 1) % FP_VALUES_MAX;\n+ }\n+ }\n+ }\n+}\n+\n #define VEC_OP1(ASM, EL, IN, OUT) \\\n asm(\"v2 = vmem(%0 + #0)\\n\\t\" \\\n \"v2\" #EL \" = \" #ASM \"(v2\" #EL \")\\n\\t\" \\\n@@ -175,4 +208,12 @@ static inline void test_##NAME(bool invert) \\\n check_output_b(__LINE__, BUFSIZE); \\\n }\n \n+#define float_sf(x) ({ typeof(x) _x = (x); *((float *)&(_x)); })\n+#define float_hf(x) ({ typeof(x) _x = (x); *((_Float16 *) &(_x)); })\n+#define raw_sf(x) ({ typeof(x) _x = (x); *((uint32_t *)&(_x)); })\n+#define raw_hf(x) ({ typeof(x) _x = (x); *((uint16_t *)&(_x)); })\n+#define float_hf_to_sf(x) ((float)x)\n+#define bytes_hf 2\n+#define bytes_sf 4\n+\n #endif\ndiff --git a/tests/tcg/hexagon/fp_hvx.c b/tests/tcg/hexagon/fp_hvx.c\nnew file mode 100644\nindex 0000000000..0365833753\n--- /dev/null\n+++ b/tests/tcg/hexagon/fp_hvx.c\n@@ -0,0 +1,155 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include <stdio.h>\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include <string.h>\n+#include <hexagon_types.h>\n+#include <hvx_hexagon_protos.h>\n+\n+int err;\n+#include \"hvx_misc.h\"\n+\n+#if __HEXAGON_ARCH__ > 75\n+#error \"After v75, compiler will replace some FP HVX instructions.\"\n+#endif\n+\n+/******************************************************************************\n+ * NAN handling\n+ *****************************************************************************/\n+\n+#define isnan(X) \\\n+ (sizeof(X) == bytes_hf ? ((raw_hf(X) & ~0x8000) > 0x7c00) : \\\n+ ((raw_sf(X) & ~(1 << 31)) > 0x7f800000UL))\n+\n+#define CHECK_NAN(A, DEF_NAN) (isnan(A) ? DEF_NAN : (A))\n+#define NAN_SF float_sf(0x7FFFFFFF)\n+#define NAN_HF float_hf(0x7FFF)\n+\n+/******************************************************************************\n+ * Binary operations\n+ *****************************************************************************/\n+\n+#define DEF_TEST_OP_2(vop, op, type_res, type_arg) \\\n+ static void test_##vop##_##type_res##_##type_arg(void) \\\n+ { \\\n+ memset(expect, 0xff, sizeof(expect)); \\\n+ memset(output, 0xff, sizeof(output)); \\\n+ for (int i = 0; i < BUFSIZE; i++) { \\\n+ HVX_Vector *hvx_output = (HVX_Vector *)&output[i]; \\\n+ HVX_Vector hvx_buffer0 = *(HVX_Vector *)&buffer0[i]; \\\n+ HVX_Vector hvx_buffer1 = *(HVX_Vector *)&buffer1[i]; \\\n+ *hvx_output = \\\n+ Q6_V##type_res##_##vop##_V##type_arg##V##type_arg(hvx_buffer0, \\\n+ hvx_buffer1); \\\n+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / bytes_##type_res; j++) { \\\n+ expect[i].type_res[j] = \\\n+ raw_##type_res(op(float_##type_arg(buffer0[i].type_arg[j]), \\\n+ float_##type_arg(buffer1[i].type_arg[j]))); \\\n+ } \\\n+ } \\\n+ check_output_##type_res(__LINE__, BUFSIZE); \\\n+ }\n+\n+#define SUM(X, Y, DEF_NAN) CHECK_NAN((X) + (Y), DEF_NAN)\n+#define SUB(X, Y, DEF_NAN) CHECK_NAN((X) - (Y), DEF_NAN)\n+#define MULT(X, Y, DEF_NAN) CHECK_NAN((X) * (Y), DEF_NAN)\n+\n+#define SUM_SF(X, Y) SUM(X, Y, NAN_SF)\n+#define SUM_HF(X, Y) SUM(X, Y, NAN_HF)\n+#define SUB_SF(X, Y) SUB(X, Y, NAN_SF)\n+#define SUB_HF(X, Y) SUB(X, Y, NAN_HF)\n+#define MULT_SF(X, Y) MULT(X, Y, NAN_SF)\n+#define MULT_HF(X, Y) MULT(X, Y, NAN_HF)\n+\n+DEF_TEST_OP_2(vadd, SUM_SF, sf, sf);\n+DEF_TEST_OP_2(vadd, SUM_HF, hf, hf);\n+DEF_TEST_OP_2(vsub, SUB_SF, sf, sf);\n+DEF_TEST_OP_2(vsub, SUB_HF, hf, hf);\n+DEF_TEST_OP_2(vmpy, MULT_SF, sf, sf);\n+DEF_TEST_OP_2(vmpy, MULT_HF, hf, hf);\n+\n+/******************************************************************************\n+ * Other tests\n+ *****************************************************************************/\n+\n+static void test_vdmpy_sf_hf(bool acc)\n+{\n+ memset(expect, 0xff, sizeof(expect));\n+\n+ for (int i = 0; i < BUFSIZE; i++) {\n+ HVX_Vector hvx_buffer0 = *(HVX_Vector *)&buffer0[i];\n+ HVX_Vector hvx_buffer1 = *(HVX_Vector *)&buffer1[i];\n+ HVX_Vector *hvx_output = (HVX_Vector *)&output[i];\n+\n+ uint32_t PREFIL_VAL = 0x111222;\n+ *hvx_output = Q6_V_vsplat_R(PREFIL_VAL);\n+\n+ if (!acc) {\n+ *hvx_output = Q6_Vsf_vdmpy_VhfVhf(hvx_buffer0, hvx_buffer1);\n+ } else {\n+ *hvx_output = Q6_Vsf_vdmpyacc_VsfVhfVhf(*hvx_output, hvx_buffer0,\n+ hvx_buffer1);\n+ }\n+\n+ for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {\n+ float a1 = float_hf_to_sf(float_hf(buffer0[i].hf[2 * j + 1]));\n+ float a2 = float_hf_to_sf(float_hf(buffer0[i].hf[2 * j]));\n+ float a3 = float_hf_to_sf(float_hf(buffer1[i].hf[2 * j + 1]));\n+ float a4 = float_hf_to_sf(float_hf(buffer1[i].hf[2 * j]));\n+ /*\n+ * Note, IEEE FP specifies +0.0 + -0.0 == +0.0. So we use -0.0 in\n+ * the default case to preserve the zero sign.\n+ */\n+ float prev = acc ? float_sf(PREFIL_VAL) : -0.0;\n+ expect[i].sf[j] = raw_sf(CHECK_NAN((a1 * a3) + (a2 * a4) + prev, NAN_SF));\n+ }\n+ }\n+ check_output_sf(__LINE__, BUFSIZE);\n+}\n+\n+static void test_new(void)\n+{\n+ asm volatile(\"r0 = #0x2\\n\"\n+ \"v0 = vsplat(r0)\\n\"\n+ \"vmem(%1 + #0) = v0\\n\"\n+ \"r1 = #0x1\\n\"\n+ \"v1 = vsplat(r1)\\n\"\n+ \"v2 = vsplat(r1)\\n\"\n+ \"{\\n\"\n+ \" v0.sf = vadd(v1.sf, v2.sf)\\n\"\n+ \" vmem(%0 + #0) = v0.new\\n\"\n+ \"}\\n\"\n+ :\n+ : \"r\"(output), \"r\"(expect)\n+ : \"r0\", \"r1\", \"v0\", \"v1\", \"v2\", \"memory\");\n+ check_output_w(__LINE__, 1);\n+}\n+\n+int main(void)\n+{\n+ init_buffers_fp();\n+\n+ /* add/sub */\n+ test_vadd_sf_sf();\n+ test_vadd_hf_hf();\n+ test_vsub_sf_sf();\n+ test_vsub_hf_hf();\n+\n+ /* multiply */\n+ test_vmpy_sf_sf();\n+ test_vmpy_hf_hf();\n+\n+ /* dot product */\n+ test_vdmpy_sf_hf(false);\n+ test_vdmpy_sf_hf(true);\n+\n+ test_new();\n+\n+ puts(err ? \"FAIL\" : \"PASS\");\n+ return err ? 1 : 0;\n+}\ndiff --git a/tests/tcg/hexagon/fp_hvx_disabled.c b/tests/tcg/hexagon/fp_hvx_disabled.c\nnew file mode 100644\nindex 0000000000..388a42e2b7\n--- /dev/null\n+++ b/tests/tcg/hexagon/fp_hvx_disabled.c\n@@ -0,0 +1,57 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include <stdio.h>\n+#include <string.h>\n+#include <hexagon_types.h>\n+#include <hvx_hexagon_protos.h>\n+\n+int err;\n+#include \"hvx_misc.h\"\n+\n+static void test_disabled(void)\n+{\n+ memset(output, 0xAA, sizeof(output));\n+ memset(expect, 0, sizeof(expect));\n+ asm volatile(\"r0 = #0xff\\n\"\n+ \"v0 = vsplat(r0)\\n\"\n+ \"r1 = #0x1\\n\"\n+ \"v1 = vsplat(r1)\\n\"\n+ \"v2 = vsplat(r1)\\n\"\n+ \"v0.sf = vadd(v1.sf, v2.sf)\\n\"\n+ \"vmem(%0 + #0) = v0\\n\"\n+ :\n+ : \"r\"(output)\n+ : \"r0\", \"r1\", \"v0\", \"v1\", \"v2\", \"memory\");\n+ check_output_w(__LINE__, 1);\n+}\n+\n+static void test_disabled_with_new(void)\n+{\n+ memset(output, 0xAA, sizeof(output));\n+ memset(expect, 0, sizeof(expect));\n+ asm volatile(\"r0 = #0xff\\n\"\n+ \"v0 = vsplat(r0)\\n\"\n+ \"r1 = #0x1\\n\"\n+ \"v1 = vsplat(r1)\\n\"\n+ \"v2 = vsplat(r1)\\n\"\n+ \"{\\n\"\n+ \" v0.sf = vadd(v1.sf, v2.sf)\\n\"\n+ \" vmem(%0 + #0) = v0.new\\n\"\n+ \"}\\n\"\n+ :\n+ : \"r\"(output)\n+ : \"r0\", \"r1\", \"v0\", \"v1\", \"v2\", \"memory\");\n+ check_output_w(__LINE__, 1);\n+}\n+\n+int main(void)\n+{\n+ test_disabled();\n+ test_disabled_with_new();\n+ puts(err ? \"FAIL\" : \"PASS\");\n+ return err ? 1 : 0;\n+}\ndiff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile.target\nindex 549c95082f..789721bdac 100644\n--- a/tests/tcg/hexagon/Makefile.target\n+++ b/tests/tcg/hexagon/Makefile.target\n@@ -50,6 +50,8 @@ HEX_TESTS += vector_add_int\n HEX_TESTS += scatter_gather\n HEX_TESTS += hvx_misc\n HEX_TESTS += hvx_histogram\n+HEX_TESTS += fp_hvx\n+HEX_TESTS += fp_hvx_disabled\n HEX_TESTS += invalid-slots\n HEX_TESTS += invalid-encoding\n HEX_TESTS += multiple-writes\n@@ -126,6 +128,12 @@ v68_hvx: CFLAGS += -mhvx -Wno-unused-function\n v69_hvx: v69_hvx.c hvx_misc.h\n v69_hvx: CFLAGS += -mhvx -Wno-unused-function\n v73_scalar: CFLAGS += -Wno-unused-function\n+fp_hvx: fp_hvx.c hvx_misc.h\n+fp_hvx: CFLAGS += -mhvx -mhvx-ieee-fp\n+fp_hvx_disabled: fp_hvx_disabled.c hvx_misc.h\n+fp_hvx_disabled: CFLAGS += -mhvx -mhvx-ieee-fp\n+\n+run-fp_hvx_disabled: QEMU_OPTS += -cpu v73,ieee-fp=false\n \n hvx_histogram: hvx_histogram.c hvx_histogram_row.S\n \t$(CC) $(CFLAGS) $(CROSS_CC_GUEST_CFLAGS) $^ -o $@ $(LDFLAGS)\n", "prefixes": [ "v3", "12/16" ] }