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GET /api/1.0/patches/2221191/?format=api
{ "id": 2221191, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2221191/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260408041953.1899532-9-brian.cain@oss.qualcomm.com>", "date": "2026-04-08T04:19:33", "name": "[v4,08/28] target/hexagon: Implement software interrupt", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "79393c74144cb8f0fa632e550140aa7bfee468ea", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/1.0/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408041953.1899532-9-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 499179, "url": "http://patchwork.ozlabs.org/api/1.0/series/499179/?format=api", "date": "2026-04-08T04:19:31", "name": "Hexagon system emulation - Part 2/3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499179/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221191/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=krOJy5Zv;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=HmLDUfH0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n 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a92af1059eb24-12bfb74c9bcmr10592536c88.22.1775622017155;\n Tue, 07 Apr 2026 21:20:17 -0700 (PDT)", "by 2002:a05:7022:2221:b0:127:33e0:ea33 with SMTP id\n a92af1059eb24-12bfb74c9bcmr10592523c88.22.1775622016542;\n Tue, 07 Apr 2026 21:20:16 -0700 (PDT)" ], "From": "Brian Cain <brian.cain@oss.qualcomm.com>", "To": "qemu-devel@nongnu.org", "Cc": "brian.cain@oss.qualcomm.com, philmd@linaro.org, ltaylorsimpson@gmail.com,\n matheus.bernardino@oss.qualcomm.com, marco.liebel@oss.qualcomm.com,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com, ale@rev.ng,\n anjo@rev.ng, Brian Cain <bcain@quicinc.com>,\n Mike Lambert <mlambert@quicinc.com>", "Subject": "[PATCH v4 08/28] target/hexagon: Implement software interrupt", "Date": "Tue, 7 Apr 2026 21:19:33 -0700", "Message-Id": "<20260408041953.1899532-9-brian.cain@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260408041953.1899532-1-brian.cain@oss.qualcomm.com>", "References": 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"X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nCo-authored-by: Mike Lambert <mlambert@quicinc.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/hexswi.h | 17 +++\n target/hexagon/cpu.c | 1 +\n target/hexagon/hexswi.c | 267 ++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 285 insertions(+)\n create mode 100644 target/hexagon/hexswi.h\n create mode 100644 target/hexagon/hexswi.c", "diff": "diff --git a/target/hexagon/hexswi.h b/target/hexagon/hexswi.h\nnew file mode 100644\nindex 00000000000..48c1ae6e4c1\n--- /dev/null\n+++ b/target/hexagon/hexswi.h\n@@ -0,0 +1,17 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HEXSWI_H\n+#define HEXSWI_H\n+\n+\n+#include \"cpu.h\"\n+\n+void hexagon_cpu_do_interrupt(CPUState *cpu);\n+void register_trap_exception(CPUHexagonState *env, int type, int imm,\n+ uint32_t PC);\n+\n+#endif /* HEXSWI_H */\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex fe7bb198d72..0670225d858 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -34,6 +34,7 @@\n #include \"sys_macros.h\"\n #include \"accel/tcg/cpu-ldst.h\"\n #include \"qemu/main-loop.h\"\n+#include \"hex_interrupts.h\"\n #endif\n \n static void hexagon_v66_cpu_init(Object *obj) { }\ndiff --git a/target/hexagon/hexswi.c b/target/hexagon/hexswi.c\nnew file mode 100644\nindex 00000000000..6dc3c91586e\n--- /dev/null\n+++ b/target/hexagon/hexswi.c\n@@ -0,0 +1,267 @@\n+/*\n+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"cpu.h\"\n+#include \"cpu_helper.h\"\n+#include \"exec/helper-proto.h\"\n+#include \"qemu/log.h\"\n+#include \"qemu/main-loop.h\"\n+#include \"arch.h\"\n+#include \"internal.h\"\n+#include \"macros.h\"\n+#include \"sys_macros.h\"\n+#include \"tcg/tcg-op.h\"\n+#include \"hex_mmu.h\"\n+#include \"hexswi.h\"\n+#include \"hw/hexagon/hexagon_globalreg.h\"\n+\n+#ifdef CONFIG_USER_ONLY\n+#error \"This file is only used in system emulation\"\n+#endif\n+\n+static void set_addresses(CPUHexagonState *env, uint32_t pc_offset,\n+ uint32_t exception_index)\n+\n+{\n+ HexagonCPU *cpu = env_archcpu(env);\n+ uint32_t evb = cpu->globalregs ?\n+ hexagon_globalreg_read(cpu->globalregs, HEX_SREG_EVB,\n+ env->threadId) :\n+ cpu->boot_addr;\n+ env->t_sreg[HEX_SREG_ELR] = env->gpr[HEX_REG_PC] + pc_offset;\n+ env->gpr[HEX_REG_PC] = evb | (exception_index << 2);\n+}\n+\n+static const char *event_name[] = {\n+ [HEX_EVENT_RESET] = \"HEX_EVENT_RESET\",\n+ [HEX_EVENT_IMPRECISE] = \"HEX_EVENT_IMPRECISE\",\n+ [HEX_EVENT_PRECISE] = \"HEX_EVENT_PRECISE\",\n+ [HEX_EVENT_TLB_MISS_X] = \"HEX_EVENT_TLB_MISS_X\",\n+ [HEX_EVENT_TLB_MISS_RW] = \"HEX_EVENT_TLB_MISS_RW\",\n+ [HEX_EVENT_TRAP0] = \"HEX_EVENT_TRAP0\",\n+ [HEX_EVENT_TRAP1] = \"HEX_EVENT_TRAP1\",\n+ [HEX_EVENT_FPTRAP] = \"HEX_EVENT_FPTRAP\",\n+ [HEX_EVENT_DEBUG] = \"HEX_EVENT_DEBUG\",\n+ [HEX_EVENT_INT0] = \"HEX_EVENT_INT0\",\n+ [HEX_EVENT_INT1] = \"HEX_EVENT_INT1\",\n+ [HEX_EVENT_INT2] = \"HEX_EVENT_INT2\",\n+ [HEX_EVENT_INT3] = \"HEX_EVENT_INT3\",\n+ [HEX_EVENT_INT4] = \"HEX_EVENT_INT4\",\n+ [HEX_EVENT_INT5] = \"HEX_EVENT_INT5\",\n+ [HEX_EVENT_INT6] = \"HEX_EVENT_INT6\",\n+ [HEX_EVENT_INT7] = \"HEX_EVENT_INT7\",\n+ [HEX_EVENT_INT8] = \"HEX_EVENT_INT8\",\n+ [HEX_EVENT_INT9] = \"HEX_EVENT_INT9\",\n+ [HEX_EVENT_INTA] = \"HEX_EVENT_INTA\",\n+ [HEX_EVENT_INTB] = \"HEX_EVENT_INTB\",\n+ [HEX_EVENT_INTC] = \"HEX_EVENT_INTC\",\n+ [HEX_EVENT_INTD] = \"HEX_EVENT_INTD\",\n+ [HEX_EVENT_INTE] = \"HEX_EVENT_INTE\",\n+ [HEX_EVENT_INTF] = \"HEX_EVENT_INTF\"\n+};\n+\n+void hexagon_cpu_do_interrupt(CPUState *cs)\n+\n+{\n+ CPUHexagonState *env = cpu_env(cs);\n+ uint32_t ssr;\n+\n+ BQL_LOCK_GUARD();\n+\n+ qemu_log_mask(CPU_LOG_INT,\n+ \"\\t%s: event 0x%02x:%s, cause 0x%\" PRIx32 \"(%\" PRIu32 \")\\n\",\n+ __func__, (unsigned)cs->exception_index,\n+ event_name[cs->exception_index], env->cause_code,\n+ env->cause_code);\n+\n+ env->llsc_addr = ~0;\n+\n+ ssr = env->t_sreg[HEX_SREG_SSR];\n+ if (GET_SSR_FIELD(SSR_EX, ssr) == 1) {\n+ HexagonCPU *cpu = env_archcpu(env);\n+ if (cpu->globalregs) {\n+ hexagon_globalreg_write(cpu->globalregs, HEX_SREG_DIAG,\n+ env->cause_code, env->threadId);\n+ }\n+ env->cause_code = HEX_CAUSE_DOUBLE_EXCEPT;\n+ cs->exception_index = HEX_EVENT_PRECISE;\n+ }\n+\n+ switch (cs->exception_index) {\n+ case HEX_EVENT_TRAP0:\n+ if (env->cause_code == 0) {\n+ qemu_log_mask(LOG_UNIMP,\n+ \"trap0 is unhandled, no semihosting available\\n\");\n+ }\n+\n+ hexagon_ssr_set_cause(env, env->cause_code);\n+ set_addresses(env, 4, cs->exception_index);\n+ break;\n+\n+ case HEX_EVENT_TRAP1:\n+ hexagon_ssr_set_cause(env, env->cause_code);\n+ set_addresses(env, 4, cs->exception_index);\n+ break;\n+\n+ case HEX_EVENT_TLB_MISS_X:\n+ switch (env->cause_code) {\n+ case HEX_CAUSE_TLBMISSX_CAUSE_NORMAL:\n+ case HEX_CAUSE_TLBMISSX_CAUSE_NEXTPAGE:\n+ qemu_log_mask(CPU_LOG_MMU,\n+ \"TLB miss EX exception (0x%02x) caught: \"\n+ \"Cause code (0x%\" PRIx32 \") \"\n+ \"TID = 0x%\" PRIx32 \", PC = 0x%\" PRIx32\n+ \", BADVA = 0x%\" PRIx32 \"\\n\",\n+ (unsigned)cs->exception_index,\n+ env->cause_code, env->threadId,\n+ env->gpr[HEX_REG_PC],\n+ env->t_sreg[HEX_SREG_BADVA]);\n+\n+ hexagon_ssr_set_cause(env, env->cause_code);\n+ set_addresses(env, 0, cs->exception_index);\n+ break;\n+\n+ default:\n+ cpu_abort(cs,\n+ \"1:Hexagon exception %d/0x%02x: \"\n+ \"Unknown cause code %\" PRIu32 \"/0x%\" PRIx32 \"\\n\",\n+ cs->exception_index, (unsigned)cs->exception_index,\n+ env->cause_code,\n+ env->cause_code);\n+ break;\n+ }\n+ break;\n+\n+ case HEX_EVENT_TLB_MISS_RW:\n+ switch (env->cause_code) {\n+ case HEX_CAUSE_TLBMISSRW_CAUSE_READ:\n+ case HEX_CAUSE_TLBMISSRW_CAUSE_WRITE:\n+ qemu_log_mask(CPU_LOG_MMU,\n+ \"TLB miss RW exception (0x%02x) caught: \"\n+ \"Cause code (0x%\" PRIx32 \") \"\n+ \"TID = 0x%\" PRIx32 \", PC = 0x%\" PRIx32\n+ \", BADVA = 0x%\" PRIx32 \"\\n\",\n+ (unsigned)cs->exception_index,\n+ env->cause_code, env->threadId,\n+ env->gpr[HEX_REG_PC],\n+ env->t_sreg[HEX_SREG_BADVA]);\n+\n+ hexagon_ssr_set_cause(env, env->cause_code);\n+ set_addresses(env, 0, cs->exception_index);\n+ /* env->sreg[HEX_SREG_BADVA] is set when the exception is raised */\n+ break;\n+\n+ default:\n+ cpu_abort(cs,\n+ \"2:Hexagon exception %d/0x%02x: \"\n+ \"Unknown cause code %\" PRIu32 \"/0x%\" PRIx32 \"\\n\",\n+ cs->exception_index, (unsigned)cs->exception_index,\n+ env->cause_code,\n+ env->cause_code);\n+ break;\n+ }\n+ break;\n+\n+ case HEX_EVENT_FPTRAP:\n+ hexagon_ssr_set_cause(env, env->cause_code);\n+ set_addresses(env, 0, cs->exception_index);\n+ break;\n+\n+ case HEX_EVENT_DEBUG:\n+ hexagon_ssr_set_cause(env, env->cause_code);\n+ set_addresses(env, 0, cs->exception_index);\n+ qemu_log_mask(LOG_UNIMP, \"single-step exception is not handled\\n\");\n+ break;\n+\n+ case HEX_EVENT_PRECISE:\n+ switch (env->cause_code) {\n+ case HEX_CAUSE_FETCH_NO_XPAGE:\n+ case HEX_CAUSE_FETCH_NO_UPAGE:\n+ case HEX_CAUSE_PRIV_NO_READ:\n+ case HEX_CAUSE_PRIV_NO_UREAD:\n+ case HEX_CAUSE_PRIV_NO_WRITE:\n+ case HEX_CAUSE_PRIV_NO_UWRITE:\n+ case HEX_CAUSE_MISALIGNED_LOAD:\n+ case HEX_CAUSE_MISALIGNED_STORE:\n+ case HEX_CAUSE_PC_NOT_ALIGNED:\n+ qemu_log_mask(CPU_LOG_MMU,\n+ \"MMU permission exception (0x%02x) caught: \"\n+ \"Cause code (0x%\" PRIx32 \") \"\n+ \"TID = 0x%\" PRIx32 \", PC = 0x%\" PRIx32\n+ \", BADVA = 0x%\" PRIx32 \"\\n\",\n+ (unsigned)cs->exception_index,\n+ env->cause_code, env->threadId,\n+ env->gpr[HEX_REG_PC],\n+ env->t_sreg[HEX_SREG_BADVA]);\n+\n+\n+ hexagon_ssr_set_cause(env, env->cause_code);\n+ set_addresses(env, 0, cs->exception_index);\n+ /* env->sreg[HEX_SREG_BADVA] is set when the exception is raised */\n+ break;\n+\n+ case HEX_CAUSE_DOUBLE_EXCEPT:\n+ case HEX_CAUSE_PRIV_USER_NO_SINSN:\n+ case HEX_CAUSE_PRIV_USER_NO_GINSN:\n+ case HEX_CAUSE_INVALID_OPCODE:\n+ case HEX_CAUSE_NO_COPROC_ENABLE:\n+ case HEX_CAUSE_NO_COPROC2_ENABLE:\n+ case HEX_CAUSE_UNSUPPORTED_HVX_64B:\n+ case HEX_CAUSE_REG_WRITE_CONFLICT:\n+ case HEX_CAUSE_VWCTRL_WINDOW_MISS:\n+ hexagon_ssr_set_cause(env, env->cause_code);\n+ set_addresses(env, 0, cs->exception_index);\n+ break;\n+\n+ case HEX_CAUSE_COPROC_LDST:\n+ hexagon_ssr_set_cause(env, env->cause_code);\n+ set_addresses(env, 0, cs->exception_index);\n+ break;\n+\n+ case HEX_CAUSE_STACK_LIMIT:\n+ hexagon_ssr_set_cause(env, env->cause_code);\n+ set_addresses(env, 0, cs->exception_index);\n+ break;\n+\n+ default:\n+ cpu_abort(cs,\n+ \"3:Hexagon exception %d/0x%02x: \"\n+ \"Unknown cause code %\" PRIu32 \"/0x%\" PRIx32 \"\\n\",\n+ cs->exception_index, (unsigned)cs->exception_index,\n+ env->cause_code,\n+ env->cause_code);\n+ break;\n+ }\n+ break;\n+\n+ case HEX_EVENT_IMPRECISE:\n+ qemu_log_mask(LOG_UNIMP,\n+ \"Imprecise exception: this case is not yet handled\");\n+ break;\n+\n+ default:\n+ qemu_log_mask(LOG_UNIMP,\n+ \"Hexagon Unsupported exception 0x%02x/0x%\" PRIx32 \"\\n\",\n+ (unsigned)cs->exception_index, env->cause_code);\n+ break;\n+ }\n+\n+ cs->exception_index = HEX_EVENT_NONE;\n+}\n+\n+void register_trap_exception(CPUHexagonState *env, int traptype, int imm,\n+ uint32_t PC)\n+{\n+ CPUState *cs = env_cpu(env);\n+\n+ cs->exception_index = (traptype == 0) ? HEX_EVENT_TRAP0 : HEX_EVENT_TRAP1;\n+ ASSERT_DIRECT_TO_GUEST_UNSET(env, cs->exception_index);\n+\n+ env->cause_code = imm;\n+ env->gpr[HEX_REG_PC] = PC;\n+ cpu_loop_exit(cs);\n+}\n", "prefixes": [ "v4", "08/28" ] }