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GET /api/1.0/patches/2221159/?format=api
{ "id": 2221159, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2221159/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260408013309.56122-2-richard.henderson@linaro.org>", "date": "2026-04-08T01:33:08", "name": "[1/2] linux-user/arm: Improve get_user_code_u32 and usage", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7e831fe50bc4923412b7e54e1b633d95bc7bbedd", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.0/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408013309.56122-2-richard.henderson@linaro.org/mbox/", "series": [ { "id": 499178, "url": "http://patchwork.ozlabs.org/api/1.0/series/499178/?format=api", "date": "2026-04-08T01:33:09", "name": "target/arm: Remove bswap_code", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499178/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221159/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=VNx47wmb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4frY8G6GT1z1xv0\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 09 Apr 2026 05:31:10 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wAYW7-00068q-EV; Wed, 08 Apr 2026 15:24:47 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wAY6s-0007Gt-VK\n for qemu-devel@nongnu.org; Wed, 08 Apr 2026 14:58:42 -0400", "from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wAHnG-0006Vh-O6\n for qemu-devel@nongnu.org; Tue, 07 Apr 2026 21:33:25 -0400", "by mail-pj1-x102d.google.com with SMTP id\n 98e67ed59e1d1-3590042fa8eso4034483a91.1\n for <qemu-devel@nongnu.org>; Tue, 07 Apr 2026 18:33:21 -0700 (PDT)", "from stoup.. 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[124.150.69.109])\n by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b2745c480dsm238277395ad.0.2026.04.07.18.33.16\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 07 Apr 2026 18:33:18 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1775611999; x=1776216799; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=oP/1GRjBSCthp+KAd33rcbtQgDmB+jnc/jSoYFA5Kjg=;\n b=VNx47wmbY0xkin4whYLB/Fs6KNwwAJFnz1IV4/ikKXPctmRRft81Lwt+BNAYzdG9eb\n E7z+yiqMwOPsCNmjVJluCLXIKAX9E2MdM+ocL5uLpJvrM5NEhhIIr5kB15g+Qd9Lbmbu\n trzP4fswoagntO+S6PN4+k7iSpk32oWiLKugR+I3kj99HB2HKCJnfaME4hQNUHeGoGgd\n W+uRFDDQJ4+liqB1csxihkvRMCtUhWrKHvhAdNjNYJNEbPuIvz7ew/iEaRYDclFHSdtc\n ampZJPiO3yucLis0ENKCN75+ygGhAKUQ7BEDzXAxg1s6eJSGq0td3itQTvCUkvGRDn1D\n lqkQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1775611999; x=1776216799;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=oP/1GRjBSCthp+KAd33rcbtQgDmB+jnc/jSoYFA5Kjg=;\n b=Q6F8TzxbBDdPpyDHoU0PKLBaSd9g3SAb4L9Tgf3QwZ+oBjSD45MW/WVeNhKLqbgNSY\n g19JmVsLQJA6heicd3FXE7Ye+BN9xPJO9GaFZpSwvOSI7rHZdWtg4w85tB2t7kB6xBD3\n SHDMp1k1lmXAo2+itnk+7npE/zlxPrnB0PoNKB4TReGJdGMsFQIq+xqd5C5a6oruWr10\n cjm3Aw8/hWeTQUPxDZlMOH02CwMums5WTvjBRH6yi4jkTr4o1xwWRm9b21yZLy4T9OMc\n lzJxkh4iXSDeKVWAPLLtRthkmXOqU+EasaaNDFAzU1PC/igCrOFHGWXrvXgro6gi+vlW\n 72fA==", "X-Gm-Message-State": "AOJu0YxkY4tPcu/BBwCIRqcpPG00QdwAmfg3y8DsHXDbT1WB1g9IUfOb\n XwIbpodrdyqitnpH2KzHDteA/8NviZvcP+hXIZZCVWTQje+Jw6ktPWUxHLPDOUE9lZUI82jHdq+\n PzX9lMEc=", "X-Gm-Gg": "AeBDietN/5zdvdV1wpG4gcHAZ1Cj5gaA6jhySrKqhTdwMc0bwYVJ1UvmrWWxPR3EP/w\n FBzbAe6pZEsL/RziDGeNvQLOipNzbuap2kam+4wRS4VngxMZ6KwK1jBaWuAu1X+c1kxQ5hZPf/Q\n rWoMprJ9EgTBbQ96OBMwLEC1dsOiQZTbGh4yeOtxkKUnCqOlO3CFFl74hVCw0LZtKDWWJId11uR\n izlY3ajPH/bhvVamN2weyPEmEmirhsTekYSYPA1htfNJWZkTQQt/tlbmSJX5I4s9EArdJq5ROn/\n g/hirhyDlPdNLOr5kLpQnfaL2mv6CMQIp69xWew6oXzVvdOodXAqvWpk6hgcTWMvTlE42adWDxY\n +OCWWgYy5trkSHZhJuGRJ1opwrUtKmW+P11u1JlExwzLsELEcYWvxXxd/VkGW1hy5n5EC1IsAP7\n Y6wu/+gBY5KlIpQ+ErSTmZYZPz7+GZbbNp9doKisqQzYDSPF+dnt/fXidW", "X-Received": "by 2002:a17:903:37ce:b0:2b2:481b:de5f with SMTP id\n d9443c01a7336-2b28163b27dmr196144595ad.5.1775611999145;\n Tue, 07 Apr 2026 18:33:19 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "pierrick.bouvier@linaro.org,\n\tqemu-arm@nongnu.org", "Subject": "[PATCH 1/2] linux-user/arm: Improve get_user_code_u32 and usage", "Date": "Wed, 8 Apr 2026 11:33:08 +1000", "Message-ID": "<20260408013309.56122-2-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260408013309.56122-1-richard.henderson@linaro.org>", "References": "<20260408013309.56122-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::102d;\n envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Force a little-endian load before applying SCTLR.B.\nHandle the BE32 swap correctly in thumb mode. This\nfixes a bug with its later usage in insn_is_linux_bkpt.\n\nHandle lock_user failure: in one case by simply falling back\nto the original SIGILL and the other by raising SIGSEGV.\n\nSigned-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n linux-user/arm/cpu_loop.c | 64 ++++++++++++++++++++++++---------------\n 1 file changed, 40 insertions(+), 24 deletions(-)", "diff": "diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c\nindex 19874f4c72..419136fdee 100644\n--- a/linux-user/arm/cpu_loop.c\n+++ b/linux-user/arm/cpu_loop.c\n@@ -29,13 +29,34 @@\n #include \"user/page-protection.h\"\n #include \"target/arm/syndrome.h\"\n \n-#define get_user_code_u32(x, gaddr, env) \\\n- ({ abi_long __r = get_user_u32((x), (gaddr)); \\\n- if (!__r && bswap_code(arm_sctlr_b(env))) { \\\n- (x) = bswap32(x); \\\n- } \\\n- __r; \\\n- })\n+static bool get_user_code_u32(uint32_t *ret, uint32_t va, CPUARMState *env)\n+{\n+ uint32_t insn, *hptr;\n+\n+ hptr = lock_user(VERIFY_READ, va, sizeof(uint32_t), 1);\n+ if (!hptr) {\n+ *ret = 0;\n+ return false;\n+ }\n+\n+ /* Load as little-endian by default. */\n+ __get_user_e(insn, hptr, le);\n+ unlock_user(hptr, va, 0);\n+\n+ /*\n+ * Adjust the little-endian load for BE32 as required.\n+ * In thumb mode, bswap both halfwords by bswap of word then\n+ * swapping the halfwords again to restore the original order.\n+ */\n+ if (arm_sctlr_b(env)) {\n+ insn = bswap32(insn);\n+ if (env->thumb) {\n+ insn = hswap32(insn);\n+ }\n+ }\n+ *ret = insn;\n+ return true;\n+}\n \n /*\n * Note that if we need to do data accesses here, they should do a\n@@ -271,7 +292,8 @@ void cpu_loop(CPUARMState *env)\n {\n CPUState *cs = env_cpu(env);\n int trapnr, si_signo, si_code;\n- unsigned int n, insn;\n+ unsigned int n;\n+ uint32_t insn;\n abi_ulong ret;\n \n for(;;) {\n@@ -284,31 +306,23 @@ void cpu_loop(CPUARMState *env)\n case EXCP_UDEF:\n case EXCP_NOCP:\n case EXCP_INVSTATE:\n- {\n- uint32_t opcode;\n-\n- /* we handle the FPU emulation here, as Linux */\n- /* we get the opcode */\n- /* FIXME - what to do if get_user() fails? */\n- get_user_code_u32(opcode, env->regs[15], env);\n-\n+ /* we handle the FPU emulation here, as Linux */\n+ if (get_user_code_u32(&insn, env->regs[15], env)) {\n /*\n * The Linux kernel treats some UDF patterns specially\n * to use as breakpoints (instead of the architectural\n * bkpt insn). These should trigger a SIGTRAP rather\n * than SIGILL.\n */\n- if (insn_is_linux_bkpt(opcode, env->thumb)) {\n+ if (insn_is_linux_bkpt(insn, env->thumb)) {\n goto excp_debug;\n }\n \n- if (!env->thumb && emulate_arm_fpa11(env, opcode)) {\n+ if (!env->thumb && emulate_arm_fpa11(env, insn)) {\n break;\n }\n-\n- force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN,\n- env->regs[15]);\n }\n+ force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->regs[15]);\n break;\n case EXCP_SWI:\n {\n@@ -317,14 +331,12 @@ void cpu_loop(CPUARMState *env)\n if (env->thumb) {\n /* Thumb is always EABI style with syscall number in r7 */\n n = env->regs[7];\n- } else {\n+ } else if (get_user_code_u32(&insn, env->regs[15] - 4, env)) {\n /*\n * Equivalent of kernel CONFIG_OABI_COMPAT: read the\n * Arm SVC insn to extract the immediate, which is the\n * syscall number in OABI.\n */\n- /* FIXME - what to do if get_user() fails? */\n- get_user_code_u32(insn, env->regs[15] - 4, env);\n n = insn & 0xffffff;\n if (n == 0) {\n /* zero immediate: EABI, syscall number in r7 */\n@@ -340,6 +352,10 @@ void cpu_loop(CPUARMState *env)\n n ^= ARM_SYSCALL_BASE;\n env->eabi = false;\n }\n+ } else {\n+ /* Failed to re-load instruction. */\n+ force_sig_fault(TARGET_SIGSEGV, 0, env->regs[15] - 4);\n+ break;\n }\n \n if (n > ARM_NR_BASE) {\n", "prefixes": [ "1/2" ] }