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GET /api/1.0/patches/2221107/?format=api
{ "id": 2221107, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2221107/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<99bac24648fdd5c5903e057eb4c9208d851070a4.1775665981.git.matheus.bernardino@oss.qualcomm.com>", "date": "2026-04-08T16:37:00", "name": "[v3,09/16] target/hexagon: add v68 HVX IEEE float conversion insns", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "88148d5134d6e8ef95cdd20751e77c73b8e3a6c4", "submitter": { "id": 90606, "url": "http://patchwork.ozlabs.org/api/1.0/people/90606/?format=api", "name": "Matheus Tavares Bernardino", "email": "matheus.bernardino@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/99bac24648fdd5c5903e057eb4c9208d851070a4.1775665981.git.matheus.bernardino@oss.qualcomm.com/mbox/", "series": [ { "id": 499185, "url": "http://patchwork.ozlabs.org/api/1.0/series/499185/?format=api", "date": "2026-04-08T16:36:53", "name": "hexagon: add missing HVX float instructions", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/499185/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221107/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=I1Naz9yr;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com 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8kb8kx350Ka1PY5tblfgQ2rISIl5blpx6HxWEODz6518g2zyzX8BGt9AwnQst9827nUb655h456\n 3v++GJBw3nZIVyb7VZBhpimc2KxS52sW/pAQ7XUZT2NEw0k6kV2sm6sY4gmlwA0MtbgZ9Ez2itt\n fqelMbV0QV", "X-Received": [ "by 2002:a05:7022:2520:b0:12a:6ab7:3f71 with SMTP id\n a92af1059eb24-12c28bd4e16mr71220c88.7.1775666239035;\n Wed, 08 Apr 2026 09:37:19 -0700 (PDT)", "by 2002:a05:7022:2520:b0:12a:6ab7:3f71 with SMTP id\n a92af1059eb24-12c28bd4e16mr71198c88.7.1775666238299;\n Wed, 08 Apr 2026 09:37:18 -0700 (PDT)" ], "From": "Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>", "To": "qemu-devel@nongnu.org", "Cc": "richard.henderson@linaro.org, ale@rev.ng, anjo@rev.ng,\n brian.cain@oss.qualcomm.com, ltaylorsimpson@gmail.com,\n marco.liebel@oss.qualcomm.com, philmd@linaro.org,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com", "Subject": "[PATCH v3 09/16] target/hexagon: add v68 HVX IEEE float conversion\n insns", "Date": "Wed, 8 Apr 2026 09:37:00 -0700", "Message-Id": "\n <99bac24648fdd5c5903e057eb4c9208d851070a4.1775665981.git.matheus.bernardino@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.37.2", "In-Reply-To": "<cover.1775665981.git.matheus.bernardino@oss.qualcomm.com>", "References": "<cover.1775665981.git.matheus.bernardino@oss.qualcomm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-GUID": "Rq4QgTynvK0m9l8IsgUw9P-SxKeqz6BY", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDA4MDE1NCBTYWx0ZWRfXwj8lSpgjWXM/\n Xu8BaIjntjUm4vvdkGymDEk/tSBLk5reKIYkNSya4D+/pb7A+VyIBBpEdLjszNPc5Jx6VbTuIIt\n vS+Yi8fHjzQWAmt4scynH1vHFqK1Q++bwzbv/x4xJLOnKKKQdLKx760bGkcttW1rGGLoUT1oW1Q\n 6WA2FN+EMmxLOVtKu7WybBPH/h6RYHC1luJMltqZgVDHBps93bOR3wXn8qPPyZ0PwsjQMta/OYf\n jXt3H330u5jax69wAP+MgXLgVTURZNHp235O3YTmY8l7yA/B2zBjFfmQONpLdB/MDtcwy7SR4op\n wMqIPOJL538z5qdtaaIiT02POOBLaASD+K2JR9eHAiQVYNyUsFhJPHG2AxOLQMyWPiL+tlAj6FO\n BAzaLELX45asEpNAziXRH+RBVc4/07ju/uXwHuAxgPLEocoE/hgKMCoG/B1Ap2rytV2QHnQrECm\n na5P6qbE1AYviFkyfzw==", "X-Authority-Analysis": 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envelope-from=matheus.bernardino@oss.qualcomm.com;\n helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add HVX IEEE floating-point conversion instructions:\n- vconv_hf_h, vconv_h_hf, vconv_sf_w, vconv_w_sf: vconv operations\n- vcvt_hf_sf, vcvt_sf_hf: float <-> half float conversions\n- vcvt_hf_b, vcvt_hf_h, vcvt_hf_ub, vcvt_hf_uh: int to half float\n- vcvt_b_hf, vcvt_h_hf, vcvt_ub_hf, vcvt_uh_hf: half float to int\n\nSigned-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>\n---\n target/hexagon/mmvec/hvx_ieee_fp.h | 4 +\n target/hexagon/mmvec/hvx_ieee_fp.c | 18 ++++\n target/hexagon/imported/mmvec/encode_ext.def | 18 ++++\n target/hexagon/imported/mmvec/ext.idef | 97 ++++++++++++++++++++\n 4 files changed, 137 insertions(+)", "diff": "diff --git a/target/hexagon/mmvec/hvx_ieee_fp.h b/target/hexagon/mmvec/hvx_ieee_fp.h\nindex ed8e4f2da9..d55837b756 100644\n--- a/target/hexagon/mmvec/hvx_ieee_fp.h\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.h\n@@ -10,6 +10,7 @@\n #include \"fpu/softfloat.h\"\n \n #define f16_to_f32(A) float16_to_float32((A), true, &env->hvx_fp_status)\n+#define f32_to_f16(A) float32_to_float16((A), true, &env->hvx_fp_status)\n \n float32 fp_mult_sf_hf(float16 a1, float16 a2, float_status *fp_status);\n float32 fp_vdmpy(float16 a1, float16 a2, float16 a3, float16 a4,\n@@ -21,4 +22,7 @@ uint32_t qf_min_sf(uint32_t a1, uint32_t a2, float_status *fp_status);\n uint16_t qf_max_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n uint16_t qf_min_hf(uint16_t a1, uint16_t a2, float_status *fp_status);\n \n+int32_t conv_w_sf(float32 a, float_status *fp_status);\n+int16_t conv_h_hf(float16 a, float_status *fp_status);\n+\n #endif\ndiff --git a/target/hexagon/mmvec/hvx_ieee_fp.c b/target/hexagon/mmvec/hvx_ieee_fp.c\nindex 868c0c5b18..0d9ff8bd5f 100644\n--- a/target/hexagon/mmvec/hvx_ieee_fp.c\n+++ b/target/hexagon/mmvec/hvx_ieee_fp.c\n@@ -68,3 +68,21 @@ float16 qf_min_hf(float16 a1, float16 a2, float_status *fp_status)\n }\n return float16_min(a1, a2, fp_status);\n }\n+\n+int32_t conv_w_sf(float32 a, float_status *fp_status)\n+{\n+ /* float32_to_int32 converts any NaN to MAX, hexagon looks at the sign. */\n+ if (float32_is_any_nan(a)) {\n+ return float32_is_neg(a) ? INT32_MIN : INT32_MAX;\n+ }\n+ return float32_to_int32_round_to_zero(a, fp_status);\n+}\n+\n+int16_t conv_h_hf(float16 a, float_status *fp_status)\n+{\n+ /* float16_to_int16 converts any NaN to MAX, hexagon looks at the sign. */\n+ if (float16_is_any_nan(a)) {\n+ return float16_is_neg(a) ? INT16_MIN : INT16_MAX;\n+ }\n+ return float16_to_int16_round_to_zero(a, fp_status);\n+}\ndiff --git a/target/hexagon/imported/mmvec/encode_ext.def b/target/hexagon/imported/mmvec/encode_ext.def\nindex 72daf8724c..c1ed1b6c23 100644\n--- a/target/hexagon/imported/mmvec/encode_ext.def\n+++ b/target/hexagon/imported/mmvec/encode_ext.def\n@@ -840,4 +840,22 @@ DEF_ENC(V6_vfneg_sf,\"00011110--0-0110PP1uuuuu011ddddd\")\n DEF_ENC(V6_vabs_hf,\"00011110--0-0110PP1uuuuu100ddddd\")\n DEF_ENC(V6_vabs_sf,\"00011110--0-0110PP1uuuuu101ddddd\")\n \n+/* IEEE FP vcvt instructions */\n+DEF_ENC(V6_vcvt_sf_hf,\"00011110--0-0100PP1uuuuu100ddddd\")\n+DEF_ENC(V6_vcvt_hf_sf,\"00011111011vvvvvPP1uuuuu001ddddd\")\n+DEF_ENC(V6_vcvt_hf_ub,\"00011110--0-0100PP1uuuuu001ddddd\")\n+DEF_ENC(V6_vcvt_hf_b,\"00011110--0-0100PP1uuuuu010ddddd\")\n+DEF_ENC(V6_vcvt_hf_uh,\"00011110--0-0100PP1uuuuu101ddddd\")\n+DEF_ENC(V6_vcvt_hf_h,\"00011110--0-0100PP1uuuuu111ddddd\")\n+DEF_ENC(V6_vcvt_uh_hf,\"00011110--0--101PP1uuuuu000ddddd\")\n+DEF_ENC(V6_vcvt_h_hf,\"00011110--0-0110PP1uuuuu000ddddd\")\n+DEF_ENC(V6_vcvt_ub_hf,\"00011111110vvvvvPP1uuuuu101ddddd\")\n+DEF_ENC(V6_vcvt_b_hf,\"00011111110vvvvvPP1uuuuu110ddddd\")\n+\n+/* IEEE FP vconv instructions */\n+DEF_ENC(V6_vconv_sf_w,\"00011110--0--101PP1uuuuu011ddddd\")\n+DEF_ENC(V6_vconv_w_sf,\"00011110--0--101PP1uuuuu001ddddd\")\n+DEF_ENC(V6_vconv_hf_h,\"00011110--0--101PP1uuuuu100ddddd\")\n+DEF_ENC(V6_vconv_h_hf,\"00011110--0--101PP1uuuuu010ddddd\")\n+\n #endif /* NO MMVEC */\ndiff --git a/target/hexagon/imported/mmvec/ext.idef b/target/hexagon/imported/mmvec/ext.idef\nindex 5312661684..3306169060 100644\n--- a/target/hexagon/imported/mmvec/ext.idef\n+++ b/target/hexagon/imported/mmvec/ext.idef\n@@ -63,6 +63,9 @@ ITERATOR_INSN_ANY_SLOT_DOUBLE_VEC(WIDTH,TAG,SYNTAX2,DESCR,CODE)\n EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS), \\\n DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n \n+#define ITERATOR_INSN_SHIFT_SLOT_FLT(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS,A_HVX_FLT), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n \n #define ITERATOR_INSN_SHIFT3_SLOT(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n EXTINSN(V6_##TAG, SYNTAX, ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VS,A_CVI_VS_3SRC,A_NOTE_SHIFT_RESOURCE,A_NOTE_NOVP,A_NOTE_VA_UNARY), \\\n@@ -3046,6 +3049,100 @@ ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vabs_hf, \"Vd32.hf=vabs(Vu32.hf)\", \\\n ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vabs_sf, \"Vd32.sf=vabs(Vu32.sf)\", \\\n \"Vector IEEE abs: sf\", VdV.hf[i] = float32_abs(VuV.hf[i]))\n \n+/* Two pipes: P2 & P3, two outputs, 16-bit */\n+#define ITERATOR_INSN_IEEE_FP_DOUBLE_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_16), \\\n+DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/* Two pipes: P2 & P3, two outputs, 32-bit output */\n+#define ITERATOR_INSN_IEEE_FP_DOUBLE_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX_DV,A_HVX_IEEE_FP_OUT_32), \\\n+ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/* Single pipe, 16-bit output */\n+#define ITERATOR_INSN_IEEE_FP_16(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16), \\\n+ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/* single pipe, output can feed 16- or 32-bit accumulate */\n+#define ITERATOR_INSN_IEEE_FP_16_32(WIDTH,TAG,SYNTAX,DESCR,CODE) \\\n+EXTINSN(V6_##TAG, SYNTAX, \\\n+ ATTRIBS(A_EXTENSION,A_HVX_IEEE_FP,A_CVI,A_CVI_VX,A_HVX_IEEE_FP_OUT_16,A_HVX_IEEE_FP_OUT_32), \\\n+ DESCR, DO_FOR_EACH_CODE(WIDTH, CODE))\n+\n+/******************************************************************************\n+ * IEEE FP convert instructions\n+ ******************************************************************************/\n+\n+ITERATOR_INSN_IEEE_FP_DOUBLE_16(32, vcvt_hf_ub, \"Vdd32.hf=vcvt(Vu32.ub)\",\n+ \"Vector IEEE cvt from int: ub widen to hf\",\n+ VddV.v[0].hf[2*i] = uint64_to_float16_scalbn(VuV.ub[4*i], float_round_nearest_even, 0);\n+ VddV.v[0].hf[2*i+1] = uint64_to_float16_scalbn(VuV.ub[4*i+1], float_round_nearest_even, 0);\n+ VddV.v[1].hf[2*i] = uint64_to_float16_scalbn(VuV.ub[4*i+2], float_round_nearest_even, 0);\n+ VddV.v[1].hf[2*i+1] = uint64_to_float16_scalbn(VuV.ub[4*i+3], float_round_nearest_even, 0))\n+\n+ITERATOR_INSN_IEEE_FP_DOUBLE_16(32, vcvt_hf_b, \"Vdd32.hf=vcvt(Vu32.b)\",\n+ \"Vector IEEE cvt from int: b widen to hf\",\n+ VddV.v[0].hf[2*i] = int64_to_float16_scalbn(VuV.b[4*i], float_round_nearest_even, 0);\n+ VddV.v[0].hf[2*i+1] = int64_to_float16_scalbn(VuV.b[4*i+1], float_round_nearest_even, 0);\n+ VddV.v[1].hf[2*i] = int64_to_float16_scalbn(VuV.b[4*i+2], float_round_nearest_even, 0);\n+ VddV.v[1].hf[2*i+1] = int64_to_float16_scalbn(VuV.b[4*i+3], float_round_nearest_even, 0))\n+\n+ITERATOR_INSN_IEEE_FP_DOUBLE_32(32, vcvt_sf_hf, \"Vdd32.sf=vcvt(Vu32.hf)\",\n+ \"Vector IEEE cvt: hf widen to sf\",\n+ VddV.v[0].sf[i] = f16_to_f32(VuV.hf[2*i]);\n+ VddV.v[1].sf[i] = f16_to_f32(VuV.hf[2*i+1]))\n+\n+ITERATOR_INSN_IEEE_FP_16(16, vcvt_hf_uh, \"Vd32.hf=vcvt(Vu32.uh)\",\n+ \"Vector IEEE cvt from int: uh to hf\",\n+ VdV.hf[i] = uint64_to_float16_scalbn(VuV.uh[i], float_round_nearest_even, 0))\n+ITERATOR_INSN_IEEE_FP_16(16, vcvt_hf_h, \"Vd32.hf=vcvt(Vu32.h)\",\n+ \"Vector IEEE cvt from int: h to hf\",\n+ VdV.hf[i] = int64_to_float16_scalbn(VuV.h[i], float_round_nearest_even, 0))\n+ITERATOR_INSN_IEEE_FP_16_32(16, vcvt_uh_hf, \"Vd32.uh=vcvt(Vu32.hf)\",\n+ \"Vector IEEE cvt to int: hf to uh\",\n+ VdV.uh[i] = float16_to_uint16_scalbn(VuV.hf[i], float_round_nearest_even, 0, &env->hvx_fp_status))\n+ITERATOR_INSN_IEEE_FP_16_32(16, vcvt_h_hf, \"Vd32.h=vcvt(Vu32.hf)\",\n+ \"Vector IEEE cvt to int: hf to h\",\n+ VdV.h[i] = float16_to_int16_scalbn(VuV.hf[i], float_round_nearest_even, 0, &env->hvx_fp_status))\n+\n+ITERATOR_INSN_IEEE_FP_16(32, vcvt_hf_sf, \"Vd32.hf=vcvt(Vu32.sf,Vv32.sf)\",\n+ \"Vector IEEE cvt: sf to hf\",\n+ VdV.hf[2*i] = f32_to_f16(VuV.sf[i]);\n+ VdV.hf[2*i+1] = f32_to_f16(VvV.sf[i]))\n+\n+ITERATOR_INSN_IEEE_FP_16_32(32, vcvt_ub_hf, \"Vd32.ub=vcvt(Vu32.hf,Vv32.hf)\", \"Vector cvt to int: hf narrow to ub\",\n+ VdV.ub[4*i] = float16_to_uint8_scalbn(VuV.hf[2*i], float_round_nearest_even, 0, &env->hvx_fp_status);\n+ VdV.ub[4*i+1] = float16_to_uint8_scalbn(VuV.hf[2*i+1], float_round_nearest_even, 0, &env->hvx_fp_status);\n+ VdV.ub[4*i+2] = float16_to_uint8_scalbn(VvV.hf[2*i], float_round_nearest_even, 0, &env->hvx_fp_status);\n+ VdV.ub[4*i+3] = float16_to_uint8_scalbn(VvV.hf[2*i+1], float_round_nearest_even, 0, &env->hvx_fp_status))\n+\n+ITERATOR_INSN_IEEE_FP_16_32(32, vcvt_b_hf, \"Vd32.b=vcvt(Vu32.hf,Vv32.hf)\",\n+ \"Vector cvt to int: hf narrow to b\",\n+ VdV.b[4*i] = float16_to_int8_scalbn(VuV.hf[2*i], float_round_nearest_even, 0, &env->hvx_fp_status);\n+ VdV.b[4*i+1] = float16_to_int8_scalbn(VuV.hf[2*i+1], float_round_nearest_even, 0, &env->hvx_fp_status);\n+ VdV.b[4*i+2] = float16_to_int8_scalbn(VvV.hf[2*i], float_round_nearest_even, 0, &env->hvx_fp_status);\n+ VdV.b[4*i+3] = float16_to_int8_scalbn(VvV.hf[2*i+1], float_round_nearest_even, 0, &env->hvx_fp_status))\n+\n+ITERATOR_INSN_SHIFT_SLOT_FLT(32, vconv_w_sf,\"Vd32.w=Vu32.sf\",\n+ \"Vector conversion of sf32 format to int w\",\n+ VdV.w[i] = conv_w_sf(VuV.sf[i], &env->hvx_fp_status))\n+\n+ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_h_hf,\"Vd32.h=Vu32.hf\",\n+ \"Vector conversion of hf16 format to int hw\",\n+ VdV.h[i] = conv_h_hf(VuV.hf[i], &env->hvx_fp_status))\n+\n+ITERATOR_INSN_SHIFT_SLOT_FLT(32, vconv_sf_w,\"Vd32.sf=Vu32.w\",\n+ \"Vector conversion of int w format to sf32\",\n+ VdV.sf[i] = int32_to_float32(VuV.w[i], &env->hvx_fp_status))\n+\n+ITERATOR_INSN_SHIFT_SLOT_FLT(16, vconv_hf_h,\"Vd32.hf=Vu32.h\",\n+ \"Vector conversion of int hw format to hf16\",\n+ VdV.hf[i] = float16_val(int16_to_float16(VuV.h[i], &env->hvx_fp_status)))\n+\n /******************************************************************************\n DEBUG Vector/Register Printing\n ******************************************************************************/\n", "prefixes": [ "v3", "09/16" ] }