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GET /api/1.0/patches/2221078/?format=api
{ "id": 2221078, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2221078/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260408041953.1899532-13-brian.cain@oss.qualcomm.com>", "date": "2026-04-08T04:19:37", "name": "[v4,12/28] target/hexagon: Implement hexagon_tlb_fill()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "77ec9479ca39fd66f9e542b281cee872f9658eb9", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/1.0/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408041953.1899532-13-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 499179, "url": "http://patchwork.ozlabs.org/api/1.0/series/499179/?format=api", "date": "2026-04-08T04:19:31", "name": "Hexagon system emulation - Part 2/3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499179/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221078/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=eh2yzwpV;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=cT9027Ig;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n 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a92af1059eb24-12bfb75688cmr9259458c88.24.1775622020913;\n Tue, 07 Apr 2026 21:20:20 -0700 (PDT)", "by 2002:a05:7022:4585:b0:128:d4db:4478 with SMTP id\n a92af1059eb24-12bfb75688cmr9259445c88.24.1775622020345;\n Tue, 07 Apr 2026 21:20:20 -0700 (PDT)" ], "From": "Brian Cain <brian.cain@oss.qualcomm.com>", "To": "qemu-devel@nongnu.org", "Cc": "brian.cain@oss.qualcomm.com, philmd@linaro.org, ltaylorsimpson@gmail.com,\n matheus.bernardino@oss.qualcomm.com, marco.liebel@oss.qualcomm.com,\n quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com, ale@rev.ng,\n anjo@rev.ng, Brian Cain <bcain@quicinc.com>", "Subject": "[PATCH v4 12/28] target/hexagon: Implement hexagon_tlb_fill()", "Date": "Tue, 7 Apr 2026 21:19:37 -0700", "Message-Id": "<20260408041953.1899532-13-brian.cain@oss.qualcomm.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260408041953.1899532-1-brian.cain@oss.qualcomm.com>", "References": "<20260408041953.1899532-1-brian.cain@oss.qualcomm.com>", "MIME-Version": "1.0", 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"X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nReviewed-by: Taylor Simpson <ltaylorsimpson@gmail.com>\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/cpu.c | 135 +++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 135 insertions(+)", "diff": "diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex adae667293d..098a3918c94 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -38,6 +38,8 @@\n #include \"qemu/main-loop.h\"\n #include \"hex_interrupts.h\"\n #include \"exec/cpu-interrupt.h\"\n+#include \"exec/target_page.h\"\n+#include \"hw/hexagon/hexagon_globalreg.h\"\n #endif\n \n static void hexagon_v66_cpu_init(Object *obj) { }\n@@ -471,6 +473,138 @@ static void hexagon_cpu_init(Object *obj)\n }\n \n #ifndef CONFIG_USER_ONLY\n+static bool get_physical_address(CPUHexagonState *env, hwaddr *phys, int *prot,\n+ uint64_t *size, int32_t *excp,\n+ uint32_t address,\n+ MMUAccessType access_type, int mmu_idx)\n+\n+{\n+ if (hexagon_cpu_mmu_enabled(env)) {\n+ return hex_tlb_find_match(env, address, access_type, phys, prot, size,\n+ excp, mmu_idx);\n+ } else {\n+ *phys = address & 0xFFFFFFFF;\n+ *prot = PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_EXEC;\n+ *size = TARGET_PAGE_SIZE;\n+ return true;\n+ }\n+}\n+\n+/* qemu seems to only want to know about TARGET_PAGE_SIZE pages */\n+static void find_qemu_subpage(vaddr *addr, hwaddr *phys, uint64_t page_size)\n+{\n+ vaddr page_start = *addr & ~((vaddr)(page_size - 1));\n+ vaddr offset = ((*addr - page_start) / TARGET_PAGE_SIZE) * TARGET_PAGE_SIZE;\n+ *addr = page_start + offset;\n+ *phys += offset;\n+}\n+\n+\n+#define INVALID_BADVA 0xbadabada\n+\n+static void set_badva_regs(CPUHexagonState *env, uint32_t VA, int slot,\n+ MMUAccessType access_type)\n+{\n+ env->t_sreg[HEX_SREG_BADVA] = VA;\n+\n+ if (access_type == MMU_INST_FETCH || slot == 0) {\n+ env->t_sreg[HEX_SREG_BADVA0] = VA;\n+ env->t_sreg[HEX_SREG_BADVA1] = INVALID_BADVA;\n+ SET_SSR_FIELD(env, SSR_V0, 1);\n+ SET_SSR_FIELD(env, SSR_V1, 0);\n+ SET_SSR_FIELD(env, SSR_BVS, 0);\n+ } else if (slot == 1) {\n+ env->t_sreg[HEX_SREG_BADVA0] = INVALID_BADVA;\n+ env->t_sreg[HEX_SREG_BADVA1] = VA;\n+ SET_SSR_FIELD(env, SSR_V0, 0);\n+ SET_SSR_FIELD(env, SSR_V1, 1);\n+ SET_SSR_FIELD(env, SSR_BVS, 1);\n+ } else {\n+ g_assert_not_reached();\n+ }\n+}\n+\n+static void raise_tlbmiss_exception(CPUState *cs, uint32_t VA, int slot,\n+ MMUAccessType access_type)\n+{\n+ CPUHexagonState *env = cpu_env(cs);\n+\n+ set_badva_regs(env, VA, slot, access_type);\n+\n+ switch (access_type) {\n+ case MMU_INST_FETCH:\n+ cs->exception_index = HEX_EVENT_TLB_MISS_X;\n+ if ((VA & ~TARGET_PAGE_MASK) == 0) {\n+ env->cause_code = HEX_CAUSE_TLBMISSX_CAUSE_NEXTPAGE;\n+ } else {\n+ env->cause_code = HEX_CAUSE_TLBMISSX_CAUSE_NORMAL;\n+ }\n+ break;\n+ case MMU_DATA_LOAD:\n+ cs->exception_index = HEX_EVENT_TLB_MISS_RW;\n+ env->cause_code = HEX_CAUSE_TLBMISSRW_CAUSE_READ;\n+ break;\n+ case MMU_DATA_STORE:\n+ cs->exception_index = HEX_EVENT_TLB_MISS_RW;\n+ env->cause_code = HEX_CAUSE_TLBMISSRW_CAUSE_WRITE;\n+ break;\n+ }\n+}\n+\n+static void raise_perm_exception(CPUState *cs, uint32_t VA, int slot,\n+ MMUAccessType access_type, int32_t excp)\n+{\n+ CPUHexagonState *env = cpu_env(cs);\n+\n+ set_badva_regs(env, VA, slot, access_type);\n+ cs->exception_index = excp;\n+}\n+\n+static const char *access_type_names[] = { \"MMU_DATA_LOAD \", \"MMU_DATA_STORE\",\n+ \"MMU_INST_FETCH\" };\n+\n+static const char *mmu_idx_names[] = { \"MMU_USER_IDX\", \"MMU_GUEST_IDX\",\n+ \"MMU_KERNEL_IDX\" };\n+\n+static bool hexagon_tlb_fill(CPUState *cs, vaddr address, int size,\n+ MMUAccessType access_type, int mmu_idx, bool probe,\n+ uintptr_t retaddr)\n+{\n+ CPUHexagonState *env = cpu_env(cs);\n+ int slot = 0;\n+ hwaddr phys;\n+ int prot = 0;\n+ uint64_t page_size = 0;\n+ int32_t excp = 0;\n+ bool ret = 0;\n+\n+ qemu_log_mask(\n+ CPU_LOG_MMU,\n+ \"%s: tid = 0x%\" PRIx32 \", pc = 0x%08\" PRIx32 \", vaddr = 0x%08\" VADDR_PRIx\n+ \", size = %d, %s,\\tprobe = %d, %s\\n\",\n+ __func__, env->threadId, env->gpr[HEX_REG_PC], address, size,\n+ access_type_names[access_type], probe, mmu_idx_names[mmu_idx]);\n+ ret = get_physical_address(env, &phys, &prot, &page_size, &excp, address,\n+ access_type, mmu_idx);\n+ if (ret) {\n+ if (!excp) {\n+ find_qemu_subpage(&address, &phys, page_size);\n+ tlb_set_page(cs, address, phys, prot, mmu_idx, TARGET_PAGE_SIZE);\n+ return ret;\n+ }\n+ if (probe) {\n+ return false;\n+ }\n+ raise_perm_exception(cs, address, slot, access_type, excp);\n+ do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC],\n+ retaddr);\n+ }\n+ if (probe) {\n+ return false;\n+ }\n+ raise_tlbmiss_exception(cs, address, slot, access_type);\n+ do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC], retaddr);\n+}\n \n static bool hexagon_cpu_exec_interrupt(CPUState *cs, int interrupt_request)\n {\n@@ -513,6 +647,7 @@ static const TCGCPUOps hexagon_tcg_ops = {\n .cpu_exec_interrupt = hexagon_cpu_exec_interrupt,\n .pointer_wrap = hexagon_pointer_wrap,\n .cpu_exec_reset = cpu_reset,\n+ .tlb_fill = hexagon_tlb_fill,\n #endif /* !CONFIG_USER_ONLY */\n };\n \n", "prefixes": [ "v4", "12/28" ] }