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GET /api/1.0/patches/2221058/?format=api
{ "id": 2221058, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2221058/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260408041953.1899532-22-brian.cain@oss.qualcomm.com>", "date": "2026-04-08T04:19:46", "name": "[v4,21/28] target/hexagon: Add next_PC, {s,g}reg writes", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2713829ca3fb03d5c78ce08579d4798085eb947b", "submitter": { "id": 89839, "url": "http://patchwork.ozlabs.org/api/1.0/people/89839/?format=api", "name": "Brian Cain", "email": "brian.cain@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260408041953.1899532-22-brian.cain@oss.qualcomm.com/mbox/", "series": [ { "id": 499179, "url": "http://patchwork.ozlabs.org/api/1.0/series/499179/?format=api", "date": "2026-04-08T04:19:31", "name": "Hexagon system emulation - Part 2/3", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/499179/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2221058/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=itEFdbl4;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=VVX8b/m2;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mx0a-0031df01.pphosted.com", "X-Spam_score_int": "-27", "X-Spam_score": "-2.8", "X-Spam_bar": "--", "X-Spam_report": "(-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Brian Cain <bcain@quicinc.com>\n\nSigned-off-by: Brian Cain <brian.cain@oss.qualcomm.com>\n---\n target/hexagon/translate.h | 2 +-\n target/hexagon/translate.c | 87 ++++++++++++++++++++++++++++++++++++--\n 2 files changed, 84 insertions(+), 5 deletions(-)", "diff": "diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h\nindex 82b327312ec..d5ea296ff26 100644\n--- a/target/hexagon/translate.h\n+++ b/target/hexagon/translate.h\n@@ -45,7 +45,7 @@ typedef struct DisasContext {\n int greg_log_idx;\n int sreg_log[SREG_WRITES_MAX];\n int sreg_log_idx;\n- TCGv_i32 t_sreg_new_value[NUM_SREGS];\n+ TCGv_i32 t_sreg_new_value[HEX_SREG_GLB_START];\n TCGv_i32 greg_new_value[NUM_GREGS];\n #endif\n int preg_log[PRED_WRITES_MAX];\ndiff --git a/target/hexagon/translate.c b/target/hexagon/translate.c\nindex 6bba135f692..a42fd771f29 100644\n--- a/target/hexagon/translate.c\n+++ b/target/hexagon/translate.c\n@@ -552,6 +552,10 @@ static void gen_start_packet(DisasContext *ctx)\n ctx->reg_log_idx = 0;\n bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS);\n bitmap_zero(ctx->predicated_regs, TOTAL_PER_THREAD_REGS);\n+#ifndef CONFIG_USER_ONLY\n+ ctx->greg_log_idx = 0;\n+ ctx->sreg_log_idx = 0;\n+#endif\n ctx->preg_log_idx = 0;\n bitmap_zero(ctx->pregs_written, NUM_PREGS);\n ctx->future_vregs_idx = 0;\n@@ -584,6 +588,24 @@ static void gen_start_packet(DisasContext *ctx)\n * gen phase, so clear it again.\n */\n bitmap_zero(ctx->pregs_written, NUM_PREGS);\n+#ifndef CONFIG_USER_ONLY\n+ for (i = 0; i < HEX_SREG_GLB_START; i++) {\n+ ctx->t_sreg_new_value[i] = NULL;\n+ }\n+ for (i = 0; i < ctx->sreg_log_idx; i++) {\n+ int reg_num = ctx->sreg_log[i];\n+ if (reg_num < HEX_SREG_GLB_START) {\n+ ctx->t_sreg_new_value[reg_num] = tcg_temp_new();\n+ }\n+ }\n+ for (i = 0; i < NUM_GREGS; i++) {\n+ ctx->greg_new_value[i] = NULL;\n+ }\n+ for (i = 0; i < ctx->greg_log_idx; i++) {\n+ int reg_num = ctx->greg_log[i];\n+ ctx->greg_new_value[reg_num] = tcg_temp_new();\n+ }\n+#endif\n \n /* Initialize the runtime state for packet semantics */\n if (need_slot_cancelled(pkt)) {\n@@ -743,6 +765,61 @@ static void gen_reg_writes(DisasContext *ctx)\n }\n }\n \n+#ifndef CONFIG_USER_ONLY\n+static void gen_greg_writes(DisasContext *ctx)\n+{\n+ int i;\n+\n+ for (i = 0; i < ctx->greg_log_idx; i++) {\n+ int reg_num = ctx->greg_log[i];\n+\n+ tcg_gen_mov_tl(hex_greg[reg_num], ctx->greg_new_value[reg_num]);\n+ }\n+}\n+\n+\n+static void gen_sreg_writes(DisasContext *ctx)\n+{\n+ int i;\n+\n+ TCGv_i32 old_reg = tcg_temp_new_i32();\n+ for (i = 0; i < ctx->sreg_log_idx; i++) {\n+ int reg_num = ctx->sreg_log[i];\n+\n+ if (reg_num == HEX_SREG_SSR) {\n+ tcg_gen_mov_tl(old_reg, hex_t_sreg[reg_num]);\n+ tcg_gen_mov_tl(hex_t_sreg[reg_num], ctx->t_sreg_new_value[reg_num]);\n+ gen_helper_modify_ssr(tcg_env, ctx->t_sreg_new_value[reg_num],\n+ old_reg);\n+ /* This can change processor state, so end the TB */\n+ ctx->base.is_jmp = DISAS_NORETURN;\n+ continue;\n+ } else if ((reg_num == HEX_SREG_STID) ||\n+ (reg_num == HEX_SREG_IMASK) ||\n+ (reg_num == HEX_SREG_IPENDAD)) {\n+ if (reg_num < HEX_SREG_GLB_START) {\n+ tcg_gen_mov_tl(old_reg, hex_t_sreg[reg_num]);\n+ tcg_gen_mov_tl(hex_t_sreg[reg_num],\n+ ctx->t_sreg_new_value[reg_num]);\n+ }\n+ /* This can change the interrupt state, so end the TB */\n+ gen_helper_pending_interrupt(tcg_env);\n+ ctx->base.is_jmp = DISAS_NORETURN;\n+ continue;\n+ } else if ((reg_num == HEX_SREG_BESTWAIT) ||\n+ (reg_num == HEX_SREG_SCHEDCFG)) {\n+ /* This can trigger resched interrupt, so end the TB */\n+ gen_helper_resched(tcg_env);\n+ ctx->base.is_jmp = DISAS_NORETURN;\n+ }\n+\n+ if (reg_num < HEX_SREG_GLB_START) {\n+ tcg_gen_mov_tl(hex_t_sreg[reg_num], ctx->t_sreg_new_value[reg_num]);\n+ }\n+ }\n+}\n+#endif\n+\n static void gen_pred_writes(DisasContext *ctx)\n {\n /* Early exit if not needed or the log is empty */\n@@ -1044,6 +1121,10 @@ static void gen_commit_packet(DisasContext *ctx)\n process_store_log(ctx);\n \n gen_reg_writes(ctx);\n+#if !defined(CONFIG_USER_ONLY)\n+ gen_greg_writes(ctx);\n+ gen_sreg_writes(ctx);\n+#endif\n gen_pred_writes(ctx);\n if (pkt->pkt_has_hvx) {\n gen_commit_hvx(ctx);\n@@ -1256,6 +1337,8 @@ void hexagon_translate_init(void)\n hex_llsc_val_i64 = tcg_global_mem_new_i64(tcg_env,\n offsetof(CPUHexagonState, llsc_val_i64), \"llsc_val_i64\");\n #ifndef CONFIG_USER_ONLY\n+ hex_cause_code = tcg_global_mem_new_i32(tcg_env,\n+ offsetof(CPUHexagonState, cause_code), \"cause_code\");\n hex_cycle_count = tcg_global_mem_new_i64(tcg_env,\n offsetof(CPUHexagonState, t_cycle_count), \"t_cycle_count\");\n #endif\n@@ -1296,8 +1379,4 @@ void hexagon_translate_init(void)\n offsetof(CPUHexagonState, vstore_pending[i]),\n vstore_pending_names[i]);\n }\n-#ifndef CONFIG_USER_ONLY\n- hex_cause_code = tcg_global_mem_new(tcg_env,\n- offsetof(CPUHexagonState, cause_code), \"cause_code\");\n-#endif\n }\n", "prefixes": [ "v4", "21/28" ] }