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GET /api/1.0/patches/2219676/?format=api
{ "id": 2219676, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2219676/?format=api", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.0/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260403-wakeirq_support-v9-3-1cbecf3b58d7@oss.qualcomm.com>", "date": "2026-04-03T17:33:35", "name": "[v9,3/3] PCI: Add support for PCIe WAKE# interrupt", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "49e31a3409757ae21b1cfe79a2fc8dc57f17c334", "submitter": { "id": 89908, "url": "http://patchwork.ozlabs.org/api/1.0/people/89908/?format=api", "name": "Krishna Chaitanya Chundru", "email": "krishna.chundru@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260403-wakeirq_support-v9-3-1cbecf3b58d7@oss.qualcomm.com/mbox/", "series": [ { "id": 498658, "url": "http://patchwork.ozlabs.org/api/1.0/series/498658/?format=api", "date": "2026-04-03T17:33:32", "name": "PCI: Add support for PCIe WAKE# interrupt", "version": 9, "mbox": "http://patchwork.ozlabs.org/series/498658/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219676/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-51834-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=gTZpm2eh;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=cClyO87Z;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=104.64.211.4; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260403-wakeirq_support-v9-3-1cbecf3b58d7@oss.qualcomm.com>", "References": "<20260403-wakeirq_support-v9-0-1cbecf3b58d7@oss.qualcomm.com>", "In-Reply-To": "<20260403-wakeirq_support-v9-0-1cbecf3b58d7@oss.qualcomm.com>", "To": "\"Rafael J. Wysocki\" <rafael@kernel.org>, Len Brown <lenb@kernel.org>,\n Pavel Machek <pavel@kernel.org>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n Danilo Krummrich <dakr@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Bartosz Golaszewski <brgl@bgdev.pl>,\n Linus Walleij <linusw@kernel.org>,\n Bartosz Golaszewski <brgl@kernel.org>, Rob Herring <robh@kernel.org>,\n Saravana Kannan <saravanak@kernel.org>,\n Linus Walleij <linusw@kernel.org>", "Cc": "linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-pci@vger.kernel.org, linux-gpio@vger.kernel.org,\n quic_vbadigan@quicinc.com, sherry.sun@nxp.com,\n driver-core@lists.linux.dev, devicetree@vger.kernel.org,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>", "X-Mailer": "b4 0.14.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1775237619; l=9559;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=BswqjKSE0ZPr7l8CqajQN/6PIFNVHGX3Hga0DwKabto=;\n b=pVJaDEIVyCYsRjLoOdV+ozcPmLpciI51NBeTwG4tfB8XVBRF6FRa0ehgQDSNsUjBcEXHth3ar\n s0c9kgZp6wJBV95/lEUubAriMtA0xndknzRipBvddEmPXjcRFTRhmT8", "X-Developer-Key": "i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=", "X-Proofpoint-GUID": "kazCUoqrTf4MnGiSXFYHHukhwplKlwGA", "X-Proofpoint-ORIG-GUID": "kazCUoqrTf4MnGiSXFYHHukhwplKlwGA", "X-Authority-Analysis": "v=2.4 cv=BO++bVQG c=1 sm=1 tr=0 ts=69cffa0d cx=c_pps\n a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22\n a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=NEAV23lmAAAA:8 a=KKAkSRfTAAAA:8\n a=XVdArZcsv8hm62BSzCUA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22\n a=cvBusfyB2V15izCimMoJ:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDAzMDE1NiBTYWx0ZWRfX+UsDOAblTkTZ\n o92omv5VTKg1ewF28MMK55FTYc53JLtClguot1dxLpoIQc0gn6xemQ688QKLu0KohwdLD1Us60B\n v4bHE+kMzrJubwc+J+38nBS4XAr0MnIPskL2ly4g0kdp/EraRtPMeQoICM/UWpQ4wGKkRCBECPH\n 3xON0ByPsgkkhq40zHlJ6e4kcU4lBP4e662ohI2dCuX5nf1vgueOZbJcnZwAblIflLcxU5IkBfK\n lMirQd6XcA9HtRj/o/8U+3KYnnzC8+kpCQH8TSwx8pJTWuJat8DCbYG2FirUkcfKYrU/wXbIwk4\n G3ZH5n5jv6qd1CgauSPczuas/naX8bQ7r6d7qWoL7gjrLs0/QdctZ54AChtGGCOcRbXk7vV4ADm\n jS4BnD+Lsxnji633ri1tXuaS9zFmm39D0zbzEbO9OPbEvSUdTFBH0XoD9sCQZ19ji1t2OLrFWcl\n qXbmrgLGO0NM4Eb3jPA==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-03_05,2026-04-03_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0\n malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 clxscore=1015\n adultscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2604030156" }, "content": "According to the PCI Express specification (PCIe r7.0, Section 5.3.3.2),\ntwo link wakeup mechanisms are defined: Beacon and WAKE#. Beacon is a\nhardware-only mechanism and is invisible to software (PCIe r7.0,\nSection 4.2.7.8.1). This change adds support for the WAKE# mechanism in\nthe PCI core.\n\nAccording to the PCIe specification, multiple WAKE# signals can exist in\na system or each component in the hierarchy could share a single WAKE#\nsignal. In configurations involving a PCIe switch, each downstream port\n(DSP) of the switch may be connected to a separate WAKE# line, allowing\neach endpoint to signal WAKE# independently. From figure 5.4 in sec\n5.3.3.2, WAKE# can also be terminated at the switch itself. To support\nthis, the WAKE# should be described in the device tree node of the\nendpoint/bridge. If all endpoints share a single WAKE# line, then each\nendpoint node should describe the same WAKE# signal or a single WAKE# in\nthe Root Port node.\n\nIn pci_device_add(), PCI framework will search for the WAKE# in device\nnode, If not found, it searches in its upstream port only if upstream port\nis Root Port. Once found, register for the wake IRQ in shared mode, as the\nWAKE# may be shared among multiple endpoints.\n\ndev_pm_set_dedicated_shared_wake_irq() associates a wakeup IRQ with a\ndevice and requests it, but the PM core keeps the IRQ disabled by default.\nThe IRQ is enabled only when the device is permitted to wake the system,\ni.e. during system suspend and after runtime suspend, and only when device\nwakeup is enabled.\n\nWhen the wake IRQ fires, the wakeirq handler invokes pm_runtime_resume() to\nbring the device back to an active power state, such as transitioning from\nD3cold to D0. Once the device is active and the link is usable, the\nendpoint may generate a PME, which is then handled by the PCI core through\nPME polling or the PCIe PME service driver to complete the wakeup of the\nendpoint.\n\nWAKE# is added in dts schema and merged based on below links.\n\nLink: https://lore.kernel.org/all/20250515090517.3506772-1-krishna.chundru@oss.qualcomm.com/\nLink: https://github.com/devicetree-org/dt-schema/pull/170\nReviewed-by: Linus Walleij <linus.walleij@linaro.org>\nSigned-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>\n---\n drivers/pci/of.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++\n drivers/pci/pci.c | 10 +++++++\n drivers/pci/pci.h | 2 ++\n drivers/pci/probe.c | 2 ++\n drivers/pci/remove.c | 1 +\n include/linux/of_pci.h | 4 +++\n include/linux/pci.h | 2 ++\n 7 files changed, 95 insertions(+)", "diff": "diff --git a/drivers/pci/of.c b/drivers/pci/of.c\nindex 9f8eb5df279ed28db7a3b2fd29c65da9975c2efa..1678e82962b78ac206829a3a1fc121b0142b993b 100644\n--- a/drivers/pci/of.c\n+++ b/drivers/pci/of.c\n@@ -7,6 +7,7 @@\n #define pr_fmt(fmt)\t\"PCI: OF: \" fmt\n \n #include <linux/cleanup.h>\n+#include <linux/gpio/consumer.h>\n #include <linux/irqdomain.h>\n #include <linux/kernel.h>\n #include <linux/pci.h>\n@@ -15,6 +16,7 @@\n #include <linux/of_address.h>\n #include <linux/of_pci.h>\n #include <linux/platform_device.h>\n+#include <linux/pm_wakeirq.h>\n #include \"pci.h\"\n \n #ifdef CONFIG_PCI\n@@ -586,6 +588,78 @@ int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin)\n \treturn irq_create_of_mapping(&oirq);\n }\n EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci);\n+\n+static void pci_configure_wake_irq(struct pci_dev *pdev, struct gpio_desc *wake)\n+{\n+\tint ret, wake_irq;\n+\n+\twake_irq = gpiod_to_irq(wake);\n+\tif (wake_irq < 0) {\n+\t\tpci_err(pdev, \"Failed to get wake irq: %d\\n\", wake_irq);\n+\t\treturn;\n+\t}\n+\n+\t/*\n+\t * dev_pm_set_dedicated_shared_wake_irq() associates a wakeup IRQ with the\n+\t * device and requests it, but the PM core keeps it disabled by default.\n+\t * The IRQ is enabled only when the device is allowed to wake the system\n+\t * (during system suspend and after runtime suspend), and only if device\n+\t * wakeup is enabled.\n+\t *\n+\t * When the wake IRQ fires, the wakeirq handler invokes pm_runtime_resume()\n+\t * to bring the device back to an active power state (e.g. from D3cold to D0).\n+\t * Once the device is active and the link is usable, the endpoint may signal\n+\t * a PME, which is then handled by the PCI core (either via PME polling or the\n+\t * PCIe PME service driver) to wakeup particular endpoint.\n+\t */\n+\tret = dev_pm_set_dedicated_shared_wake_irq(&pdev->dev, wake_irq,\n+\t\t\t\t\t\t IRQ_TYPE_LEVEL_LOW);\n+\tif (ret < 0) {\n+\t\tpci_err(pdev, \"Failed to set WAKE# IRQ: %d\\n\", ret);\n+\t\treturn;\n+\t}\n+\n+\tdevice_init_wakeup(&pdev->dev, true);\n+}\n+\n+void pci_configure_of_wake_gpio(struct pci_dev *dev)\n+{\n+\tstruct device_node *dn = pci_device_to_OF_node(dev);\n+\tstruct pci_dev *upstream;\n+\tstruct gpio_desc *gpio;\n+\n+\tif (!dn)\n+\t\treturn;\n+\n+\t/*\n+\t * The devices in a hierarchy expose wakeup capability through the 'wake-gpios'\n+\t * property defined either in the device node or in the Slot node. So first check\n+\t * for the property in device node and if not available, check in the Slot node.\n+\t */\n+\tgpio = fwnode_gpiod_get(of_fwnode_handle(dn), \"wake\",\n+\t\t\t\tGPIOD_IN | GPIOD_FLAGS_BIT_NONEXCLUSIVE, NULL);\n+\tif (IS_ERR(gpio)) {\n+\t\tupstream = pci_upstream_bridge(dev);\n+\t\tif (upstream && pci_is_root_bus(upstream->bus) && upstream->wake)\n+\t\t\tpci_configure_wake_irq(dev, upstream->wake);\n+\t} else {\n+\t\tdev->wake = gpio;\n+\t\tpci_configure_wake_irq(dev, gpio);\n+\t}\n+}\n+\n+void pci_remove_of_wake_gpio(struct pci_dev *dev)\n+{\n+\tstruct device_node *dn = pci_device_to_OF_node(dev);\n+\n+\tif (!dn)\n+\t\treturn;\n+\n+\tdev_pm_clear_wake_irq(&dev->dev);\n+\tdevice_init_wakeup(&dev->dev, false);\n+\tgpiod_put(dev->wake);\n+\tdev->wake = NULL;\n+}\n #endif\t/* CONFIG_OF_IRQ */\n \n static int pci_parse_request_of_pci_ranges(struct device *dev,\ndiff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\nindex 8479c2e1f74f1044416281aba11bf071ea89488a..3d858f36ab48a6daec645574ca9027d9d6f071de 100644\n--- a/drivers/pci/pci.c\n+++ b/drivers/pci/pci.c\n@@ -17,6 +17,7 @@\n #include <linux/lockdep.h>\n #include <linux/msi.h>\n #include <linux/of.h>\n+#include <linux/of_pci.h>\n #include <linux/pci.h>\n #include <linux/pm.h>\n #include <linux/slab.h>\n@@ -1123,6 +1124,15 @@ static inline bool platform_pci_bridge_d3(struct pci_dev *dev)\n \treturn acpi_pci_bridge_d3(dev);\n }\n \n+void platform_pci_configure_wake(struct pci_dev *dev)\n+{\n+\treturn pci_configure_of_wake_gpio(dev);\n+}\n+\n+void platform_pci_remove_wake(struct pci_dev *dev)\n+{\n+\treturn pci_remove_of_wake_gpio(dev);\n+}\n /**\n * pci_update_current_state - Read power state of given device and cache it\n * @dev: PCI device to handle.\ndiff --git a/drivers/pci/pci.h b/drivers/pci/pci.h\nindex 13d998fbacce6698514d92500dfea03cc562cdc2..65ca9551e558d2e3331fab0a968620d6b2a2522a 100644\n--- a/drivers/pci/pci.h\n+++ b/drivers/pci/pci.h\n@@ -282,6 +282,8 @@ void pci_msix_init(struct pci_dev *dev);\n bool pci_bridge_d3_possible(struct pci_dev *dev);\n void pci_bridge_d3_update(struct pci_dev *dev);\n int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);\n+void platform_pci_configure_wake(struct pci_dev *dev);\n+void platform_pci_remove_wake(struct pci_dev *dev);\n \n static inline bool pci_bus_rrs_vendor_id(u32 l)\n {\ndiff --git a/drivers/pci/probe.c b/drivers/pci/probe.c\nindex bccc7a4bdd794384b7877d453c7989941471c999..372b0d2f4531ea53c0570608306a547101d59e7b 100644\n--- a/drivers/pci/probe.c\n+++ b/drivers/pci/probe.c\n@@ -2771,6 +2771,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)\n \t/* Establish pdev->tsm for newly added (e.g. new SR-IOV VFs) */\n \tpci_tsm_init(dev);\n \n+\tplatform_pci_configure_wake(dev);\n+\n \tpci_npem_create(dev);\n \n \tpci_doe_sysfs_init(dev);\ndiff --git a/drivers/pci/remove.c b/drivers/pci/remove.c\nindex e9d519993853f92f1810d3eff9f44ca7e3e1abd9..d781b41e57c4444077075690cec926a9fe15334f 100644\n--- a/drivers/pci/remove.c\n+++ b/drivers/pci/remove.c\n@@ -35,6 +35,7 @@ static void pci_destroy_dev(struct pci_dev *dev)\n \tif (pci_dev_test_and_set_removed(dev))\n \t\treturn;\n \n+\tplatform_pci_remove_wake(dev);\n \tpci_doe_sysfs_teardown(dev);\n \tpci_npem_remove(dev);\n \ndiff --git a/include/linux/of_pci.h b/include/linux/of_pci.h\nindex 29658c0ee71ff10122760214d04ee2bab01709fd..0efd6e9cb4d3d3beaafb42ea411303139f1150d5 100644\n--- a/include/linux/of_pci.h\n+++ b/include/linux/of_pci.h\n@@ -30,12 +30,16 @@ static inline void of_pci_check_probe_only(void) { }\n \n #if IS_ENABLED(CONFIG_OF_IRQ)\n int of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin);\n+void pci_configure_of_wake_gpio(struct pci_dev *dev);\n+void pci_remove_of_wake_gpio(struct pci_dev *dev);\n #else\n static inline int\n of_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin)\n {\n \treturn 0;\n }\n+static inline void pci_configure_of_wake_gpio(struct pci_dev *dev) { }\n+static inline void pci_remove_of_wake_gpio(struct pci_dev *dev) { }\n #endif\n \n #endif\ndiff --git a/include/linux/pci.h b/include/linux/pci.h\nindex 1c270f1d512301de4d462fe7e5097c32af5c6f8d..d1e08df8a8deaa87780589f23242767fdcdba541 100644\n--- a/include/linux/pci.h\n+++ b/include/linux/pci.h\n@@ -586,6 +586,8 @@ struct pci_dev {\n \t/* These methods index pci_reset_fn_methods[] */\n \tu8 reset_methods[PCI_NUM_RESET_METHODS]; /* In priority order */\n \n+\tstruct gpio_desc *wake; /* Holds WAKE# gpio */\n+\n #ifdef CONFIG_PCIE_TPH\n \tu16\t\ttph_cap;\t/* TPH capability offset */\n \tu8\t\ttph_mode;\t/* TPH mode */\n", "prefixes": [ "v9", "3/3" ] }