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GET /api/1.0/patches/2219666/?format=api
{ "id": 2219666, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2219666/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260403162541.86608-3-sgdfkk@163.com>", "date": "2026-04-03T16:25:36", "name": "[v7,2/7] mips: loongson: lowlevel initialize", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3155f0f0ed8e0ae684bc408436177a2871cd1f11", "submitter": { "id": 92844, "url": "http://patchwork.ozlabs.org/api/1.0/people/92844/?format=api", "name": null, "email": "sgdfkk@163.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260403162541.86608-3-sgdfkk@163.com/mbox/", "series": [ { "id": 498655, "url": "http://patchwork.ozlabs.org/api/1.0/series/498655/?format=api", "date": "2026-04-03T16:25:35", "name": "add loongson mips ls1c300 initial support", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/498655/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219666/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.a=rsa-sha256\n header.s=s110527 header.b=jAm419YR;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=163.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=163.com header.i=@163.com header.b=\"jAm419YR\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=163.com", "phobos.denx.de; spf=pass smtp.mailfrom=sgdfkk@163.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fnPHN4q72z1yDH\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 04 Apr 2026 03:26:24 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id EB19684154;\n\tFri, 3 Apr 2026 18:25:57 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id DF62C84120; Fri, 3 Apr 2026 18:25:55 +0200 (CEST)", "from m16.mail.163.com (m16.mail.163.com [117.135.210.2])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 06826840BE\n for <u-boot@lists.denx.de>; Fri, 3 Apr 2026 18:25:50 +0200 (CEST)", "from server-e.. (unknown [])\n by gzsmtp3 (Coremail) with SMTP id PigvCgAnAXQF6s9pHqSgBw--.137S4;\n Sat, 04 Apr 2026 00:25:47 +0800 (CST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,HK_RANDOM_ENVFROM,\n HK_RANDOM_FROM,RCVD_IN_DNSWL_BLOCKED,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=no\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com;\n s=s110527; h=From:To:Subject:Date:Message-ID:MIME-Version; bh=bR\n gf4tHx2QPaRnplCllVjIny7siKEOzymzrQuqq67/E=; b=jAm419YRE7pe9WCyzK\n 6lUdWumg5JWj1qS86fd/jnVEP8K9VKvs7CtvHsXLWfkxzq22LC9WG3ROHDovPI0k\n j21TiJ5seEWniYjrj9bX9a8UfdGUGhbBiH/dr4hQxQU6l1KBT5+oLMOCah6w6sxz\n lY0aKa3kHUdbx+m6VRIxYm+8s=", "From": "sgdfkk@163.com", "To": "u-boot@lists.denx.de", "Cc": "Du Huanpeng <u74147@gmail.com>", "Subject": "[PATCH v7 2/7] mips: loongson: lowlevel initialize", "Date": "Sat, 4 Apr 2026 00:25:36 +0800", "Message-ID": "<20260403162541.86608-3-sgdfkk@163.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260403162541.86608-1-sgdfkk@163.com>", "References": "<20260403162541.86608-1-sgdfkk@163.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "PigvCgAnAXQF6s9pHqSgBw--.137S4", "X-Coremail-Antispam": "1Uf129KBjvJXoW3GrWrCw1rXrW8Gw1xZw45GFg_yoWxCr4Dpr\n 1jkay5tw18Ga17Wwn3KF1rKr13JFnYgryYyrnrXr48uF4xJw1xGFWqgw43tr9xXFsYyayr\n JrykXa1j939rZw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2\n 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07U9NVgUUUUU=", "X-Originating-IP": "[240e:3b0:4805:581::3001]", "X-CM-SenderInfo": "xvjgwyrn6rljoofrz/xtbC5wsLYmnP6gu8VwAA3p", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Du Huanpeng <u74147@gmail.com>\n\n- pll\n- spi controller\n- sdram\n\nSigned-off-by: Du Huanpeng <u74147@gmail.com>\n---\n .../mach-loongson/ls1c300/lowlevel_init.S | 134 ++++++++++++++++++\n arch/mips/mach-loongson/ls1c300/sdram.S | 95 +++++++++++++\n 2 files changed, 229 insertions(+)\n create mode 100644 arch/mips/mach-loongson/ls1c300/lowlevel_init.S\n create mode 100644 arch/mips/mach-loongson/ls1c300/sdram.S", "diff": "diff --git a/arch/mips/mach-loongson/ls1c300/lowlevel_init.S b/arch/mips/mach-loongson/ls1c300/lowlevel_init.S\nnew file mode 100644\nindex 00000000000..8d9ba97130c\n--- /dev/null\n+++ b/arch/mips/mach-loongson/ls1c300/lowlevel_init.S\n@@ -0,0 +1,134 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020 MediaTek Inc.\n+ *\n+ * Author: Gao Weijie <weijie.gao@mediatek.com>\n+ *\n+ * Copyright (C) 2020-2023 Du Huanpeng <u74147@gmail.com>\n+ */\n+\n+#include <config.h>\n+#include <asm-offsets.h>\n+#include <asm/cacheops.h>\n+#include <asm/regdef.h>\n+#include <asm/mipsregs.h>\n+#include <asm/addrspace.h>\n+#include <asm/asm.h>\n+#include <linux/sizes.h>\n+\n+/* PLL control register */\n+#define NAND_BASE\t0xbfe70000\n+#define START_FREQ\t0x8030\n+#define CLK_DIV_PARAM\t0x8034\n+#define CPU_THROT\t0xc010\n+\n+/* START_FREQ */\n+#define PLL_VALID\t31\n+#define Reserved_24\t24\n+#define FRAC_N\t\t16\n+#define M_PLL\t\t8\n+#define Reserved_4\t4\n+#define RST_TIME\t2\n+#define SDRAM_DIV\t0\n+ #define SDRAM_DIV2\t0\n+ #define SDRAM_DIV4\t1\n+ #define SDRAM_DIV3\t2\n+\n+/* CLK_DIV_PARAM */\n+#define PIX_DIV\t\t24\n+#define CAM_DIV\t\t16\n+#define CPU_DIV\t\t8\n+#define PIX_DIV_VALID\t5\n+#define PIX_SEL\t\t4\n+#define CAM_DIV_VALID\t3\n+#define CAM_SEL\t\t2\n+#define CPU_DIV_VALID\t1\n+#define CPU_SEL\t\t0\n+\n+/* Document:\n+ * Freq_PLL = XIN *(M_PLL + FRAC_N)/4\n+ */\n+#define XIN\t\t\t24000000\n+#define PLL_VALID_1\t\t(1<<PLL_VALID)\n+#define PREP_M_PLL(Freq_PLL)\t(((Freq_PLL * 4) / XIN) << M_PLL)\n+#define PREP_SDRAM_DIV(div)\t(div<<SDRAM_DIV)\n+#define PREP_CPU_DIV(div1)\t((0x80|div1)<<CPU_DIV | (div1&&div1)<<CPU_DIV_VALID)\n+#define PREP_PIX_DIV(div2)\t(div2<<PIX_DIV)\n+#define PREP_CAM_DIV(div3)\t(div3<<CAM_DIV)\n+\n+/* PLL @264MHz, CPU @132MHz, SDRAM @66MHz */\n+#define CFG_START_FREQ\t\t(PLL_VALID_1 | PREP_M_PLL(264000000) | SDRAM_DIV2)\n+#define CFG_CLK_DIV_PARAM\t(PREP_CPU_DIV(2) | PREP_PIX_DIV(0x24) | PREP_CAM_DIV(0x24))\n+#define CFG_CPU_THROT\t\t15\n+\n+/* SPI0 control register */\n+#define SPI0_BASE\t\t0xbfe80000\n+#define SPCR\t\t\t0\n+#define SPSR\t\t\t1\n+#define TxFIFO\t\t\t2\n+#define RxFIFO\t\t\t2\n+#define SPER\t\t\t3\n+#define SFC_PARAM\t\t4\n+ #define CLK_DIV\t\t4\n+ #define DUAL_IO\t\t3\n+ #define FAST_READ\t\t2\n+ #define BURST_EN\t\t1\n+ #define MEMORY_EN\t\t0\n+#define SFC_SOFTCS\t\t5\n+#define SFC_TIMING\t\t6\n+ #define T_FAST\t\t2\n+ #define T_CSH\t\t0\n+\n+\t.set noreorder\n+LEAF(ls1c300_pll_init)\n+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)\n+\tli\tt0, NAND_BASE\n+\tli\tt1, CFG_START_FREQ\n+\tli\tt2, CFG_CLK_DIV_PARAM\n+\tli\tt3, CFG_CPU_THROT\n+\n+\tsw\tt3, CPU_THROT (t0)\n+\tsw\tt2, CLK_DIV_PARAM (t0)\n+\tsw\tt1, START_FREQ (t0)\n+\n+\tori\tt2, 1<<CPU_SEL\n+\tsw\tt2, CLK_DIV_PARAM (t0)\n+#endif\n+\tjr\tra\n+\t nop\n+END(ls1c300_pll_init)\n+\n+LEAF(ls1c300_spi_init)\n+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)\n+\tli\tt0, SPI0_BASE\n+\tli\tt1, (1<<MEMORY_EN) | (1<<BURST_EN) | (1<<FAST_READ) | (1<<DUAL_IO)\n+\tsb\tt1, SFC_PARAM (t0)\n+\tli\tt2, (1<<T_FAST) | (1<<T_CSH)\n+\tsb\tt2, SFC_TIMING (t0)\n+#endif\n+\tjr\tra\n+\t nop\n+END(ls1c300_spi_init)\n+\n+NESTED(lowlevel_init, 0, ra)\n+\t/* Save ra and do real lowlevel initialization */\n+\tmove\ts0, ra\n+\t/* Setup PLL @264MHz */\n+\tPTR_LA\tt9, ls1c300_pll_init\n+\tjalr\tt9\n+\t nop\n+\n+\t/* Setup SPI Dual IO@33MHz */\n+\tPTR_LA\tt9, ls1c300_spi_init\n+\tjalr\tt9\n+\t nop\n+\n+\t/* Setup external SDRAM @66MHz */\n+\tPTR_LA\tt9, ls1c300_sdram_init\n+\tjalr\tt9\n+\t nop\n+\n+\tmove\tra, s0\n+\tjr\tra\n+\t nop\n+END(lowlevel_init)\ndiff --git a/arch/mips/mach-loongson/ls1c300/sdram.S b/arch/mips/mach-loongson/ls1c300/sdram.S\nnew file mode 100644\nindex 00000000000..0dadd41adea\n--- /dev/null\n+++ b/arch/mips/mach-loongson/ls1c300/sdram.S\n@@ -0,0 +1,95 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2020-2023 Du Huanpeng <u74147@gmail.com>\n+ */\n+\n+#include <config.h>\n+#include <asm-offsets.h>\n+#include <asm/cacheops.h>\n+#include <asm/regdef.h>\n+#include <asm/mipsregs.h>\n+#include <asm/addrspace.h>\n+#include <asm/asm.h>\n+#include <linux/sizes.h>\n+\n+/* sdram control 64 bit register */\n+#define SD_CONFIG\t0xbfd00000\n+#define SD_CONFIGHI\t0x414\n+#define SD_CONFIGLO\t0x410\n+\n+#define VALID\t\t41\n+#define HANG_UP\t\t40\n+#define DEF_SEL\t\t39\n+#define TWR\t\t37\n+#define TREF\t\t25\n+#define TRAS\t\t21\n+#define TRFC\t\t17\n+#define TRP\t\t14\n+#define TCL\t\t11\n+#define TRCD\t\t8\n+\n+#define SD_BIT\t\t6\n+ #define SD_8BIT (0<<SD_BIT)\n+ #define SD_16BIT (1<<SD_BIT)\n+ #define SD_32BIT (2<<SD_BIT)\n+#define SD_CSIZE\t3\n+ #define SD_CSIZE_512\t(0<<SD_CSIZE)\n+ #define SD_CSIZE_1K\t(1<<SD_CSIZE)\n+ #define SD_CSIZE_2K\t(2<<SD_CSIZE)\n+ #define SD_CSIZE_4K\t(3<<SD_CSIZE)\n+ #define SD_CSIZE_256\t(7<<SD_CSIZE)\n+#define SD_RSIZE\t0\n+ #define SD_RSIZE_2K\t(0<<SD_RSIZE)\n+ #define SD_RSIZE_4K\t(1<<SD_RSIZE)\n+ #define SD_RSIZE_8K\t(2<<SD_RSIZE)\n+ #define SD_RSIZE_16K\t(3<<SD_RSIZE)\n+\n+#define SD_CFG_1(tWR, tREF, tRAS, tRFC, tRP, tCL, tRCD) \\\n+\t((tWR<<TWR)|(tREF<<TREF)|(tRAS<<TRAS)|(tRFC<<TRFC)|(tRP<<TRP)|(tCL<<TCL)|(tRCD<<TRCD))\n+#define CFG_SD_0(b, c, r) \\\n+\t((b<<SD_BIT)|(c<<SD_CSIZE)|(r<<SD_RSIZE))\n+/*\n+ * recommended values by ls1c300 user manual,\n+ * tweak to fit your board.\n+ */\n+#define SD_CONFIG_133MHz\tSD_CFG_1(2, 0x818, 6, 8, 3, 3, 3)\n+#define SD_CONFIG_100MHz\tSD_CFG_1(2, 0x620, 5, 6, 2, 3, 2)\n+#define SD_CONFIG_75MHz\t\tSD_CFG_1(1, 0x494, 4, 5, 2, 2, 2)\n+#define SD_CONFIG_33MHz\t\tSD_CFG_1(1, 0x204, 2, 2, 1, 2, 1)\n+\n+#define SD_CONFIG_66MHz\t\tSD_CFG_1(1, 0x401, 4, 4, 2, 2, 2)\n+\n+#define SD_CONFIG64\t(SD_CONFIG_66MHz | SD_16BIT | SD_CSIZE_1K | SD_RSIZE_8K)\n+#define CFG_SDCONFIGHI\t(SD_CONFIG64 /(1<<32))\n+#define CFG_SDCONFIGLO\t(SD_CONFIG64 %(1<<32))\n+\n+\t.set noreorder\n+/*\n+ * Loongson ls1c300 SoC do not have onchip sram for initial stack,\n+ * initialize the external sdram on reset as early as possiable.\n+ */\n+LEAF(ls1c300_sdram_init)\n+#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)\n+\tli\tt0, SD_CONFIG\n+\tli\tt1, CFG_SDCONFIGLO\n+\tli\tt2, CFG_SDCONFIGHI\n+\n+/* store twice as the hardware manual required. */\n+\tsw\tt1, SD_CONFIGLO (t0)\n+\tsw\tt2, SD_CONFIGHI (t0)\n+\tsync\n+\n+\tsw\tt1, SD_CONFIGLO (t0)\n+\tsw\tt2, SD_CONFIGHI (t0)\n+\tsync\n+\n+\tori\tt2, 1<<(VALID-32)\n+\tsw\tt1, SD_CONFIGLO (t0)\n+\tsw\tt2, SD_CONFIGHI (t0)\n+\tsync\n+#endif\n+\tjr\tra\n+\t nop\n+END(ls1c300_sdram_init)\n+\n+\n", "prefixes": [ "v7", "2/7" ] }