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GET /api/1.0/patches/2219416/?format=api
{ "id": 2219416, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2219416/?format=api", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/1.0/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260402230626.3826719-7-grzegorz.nitka@intel.com>", "date": "2026-04-02T23:06:24", "name": "[v5,net-next,6/8] ice: implement CPI support for E825C", "commit_ref": null, "pull_url": null, "state": "handled-elsewhere", "archived": false, "hash": "3eccd940d444b8878a86df87725e84c2185726fe", "submitter": { "id": 82711, "url": "http://patchwork.ozlabs.org/api/1.0/people/82711/?format=api", "name": "Grzegorz Nitka", "email": "grzegorz.nitka@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260402230626.3826719-7-grzegorz.nitka@intel.com/mbox/", "series": [ { "id": 498564, "url": "http://patchwork.ozlabs.org/api/1.0/series/498564/?format=api", "date": "2026-04-02T23:06:18", "name": "dpll/ice: Add TXC DPLL type and full TX reference clock control for E825", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/498564/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219416/checks/", "tags": {}, "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=2e5f7/YU;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::138; 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envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=<UNKNOWN> ", "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 smtp1.osuosl.org 04366812D5", "OpenDKIM Filter v2.11.0 smtp4.osuosl.org A30B04050D" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=osuosl.org;\n\ts=default; t=1775171454;\n\tbh=X6xDNyjn4HukUgv0b0hM8BsEYw+MaX2gtYWzeBZ/+ZA=;\n\th=From:To:Date:In-Reply-To:References:Subject:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t Cc:From;\n\tb=2e5f7/YUf5vULH9hCSe4lmPe59ZcB88iDtN9+POxcj4X3HLxNa4ZUq+GhnwuKzEUD\n\t v+hZ9Le4qvZ5D08mFlyEeXAKgJ/fRBgdI+j7ZemC8q0eN3KG2fXrnIUqg5LE9PYlJO\n\t TSx5jHs0G1kbK/bE23uUfcNhh8CNm6URcHXIAb8fcy0NuITprVjbuA8Pkrdj3P+nuY\n\t Du7o8nSm3b2WNTZtrelnlZhyl6t/+w8+1ovujas8TZnzcOLKcwStsyby/Ddk/Mx0Zy\n\t RbSe4EQlKnAzLhfw2pAqbRCv+74N/AjtJjuTuhD4rTsF5kis+j77aZkFvChv6DNNBj\n\t VK9QVUB10dG2g==", "Received-SPF": "Pass (mailfrom) identity=mailfrom; client-ip=198.175.65.19;\n helo=mgamail.intel.com; envelope-from=grzegorz.nitka@intel.com;\n receiver=<UNKNOWN>", "DMARC-Filter": "OpenDMARC Filter v1.4.2 smtp4.osuosl.org A30B04050D", "X-CSE-ConnectionGUID": [ "FxzSIWcaTlq3hiDqnjkBKQ==", "NGOvUVkLRaCEiOPnlbo6tQ==" ], "X-CSE-MsgGUID": [ "/gZP7eLGSUOzOFcX+Oclsw==", "OV1TsNCbRrmTMCwmd4+C6Q==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11747\"; a=\"76123131\"", "E=Sophos;i=\"6.23,156,1770624000\"; d=\"scan'208\";a=\"76123131\"", "E=Sophos;i=\"6.23,156,1770624000\"; d=\"scan'208\";a=\"227044460\"" ], "X-ExtLoop1": "1", "From": "Grzegorz Nitka <grzegorz.nitka@intel.com>", "To": "netdev@vger.kernel.org", "Date": "Fri, 3 Apr 2026 01:06:24 +0200", "Message-Id": "<20260402230626.3826719-7-grzegorz.nitka@intel.com>", "X-Mailer": "git-send-email 2.39.3", "In-Reply-To": "<20260402230626.3826719-1-grzegorz.nitka@intel.com>", "References": "<20260402230626.3826719-1-grzegorz.nitka@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Mailman-Original-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1775171452; x=1806707452;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=OxncUXAXkexzCLewPifmJfYRwZtDvm+RnLCpTY9wiJ4=;\n b=Dlh0sDCKob1b5sTtifOyJ/fKct10Xao7AJOaJuJmgK6VI//x9DZQEGru\n 2K7Hx5SpJlvhSXaruDX4PXelt2GVJm/slqcov/vhjtvaAGek5qMDRrR2E\n z2InOE0h0TvjBoLLEqekVRAWxKT+NvbodoA8OWzuGQods6DdYfIs7eanS\n Q5817GhFZPUHWtyTkg0tzc8uY+4rnD7aYq5ky1Ajf33gKITPaI7+Z3+Nk\n d7eQ6UE4YGCh2Bgzv2PbSsv/vaHvDLTVAXynMZHnIiUeDKU8M8hrtNekL\n G4oXMg5RZp2Mn9MnDAKVsUAHcWasyWWL1EYwei/jzwZDU5pCRrwzVG0UO\n A==;", "X-Mailman-Original-Authentication-Results": [ "smtp4.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com", "smtp4.osuosl.org;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.a=rsa-sha256 header.s=Intel header.b=Dlh0sDCK" ], "Subject": "[Intel-wired-lan] [PATCH v5 net-next 6/8] ice: implement CPI\n support for E825C", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "ivecera@redhat.com, vadim.fedorenko@linux.dev, kuba@kernel.org,\n jiri@resnulli.us, edumazet@google.com, przemyslaw.kitszel@intel.com,\n richardcochran@gmail.com, donald.hunter@gmail.com,\n linux-kernel@vger.kernel.org, arkadiusz.kubalewski@intel.com,\n andrew+netdev@lunn.ch, intel-wired-lan@lists.osuosl.org, horms@kernel.org,\n Prathosh.Satish@microchip.com, anthony.l.nguyen@intel.com, pabeni@redhat.com,\n davem@davemloft.net", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Add full CPI (Converged PHY Interface) command handling required for\nE825C devices. The CPI interface allows the driver to interact with\nPHY-side control logic through the LM/PHY command registers, including\nenabling/disabling/selection of PHY reference clock.\n\nThis patch introduces:\n - a new CPI subsystem (ice_cpi.c / ice_cpi.h) implementing the CPI\n request/acknowledge state machine, including REQ/ACK protocol,\n command execution, and response handling\n - helper functions for reading/writing PHY registers over Sideband\n Queue\n - CPI command execution API (ice_cpi_exec) and a helper for enabling or\n disabling Tx reference clocks (CPI 0xF1 opcode 'Config PHY clocking')\n - addition of the non-posted write opcode (wr_np) to SBQ\n - Makefile integration to build CPI support together with the PTP stack\n\nThis provides the infrastructure necessary to support PHY-side\nconfiguration flows on E825C and is required for advanced link control\nand Tx reference clock management.\n\nReviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>\nSigned-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>\n---\n drivers/net/ethernet/intel/ice/Makefile | 2 +-\n drivers/net/ethernet/intel/ice/ice_cpi.c | 337 +++++++++++++++++++\n drivers/net/ethernet/intel/ice/ice_cpi.h | 61 ++++\n drivers/net/ethernet/intel/ice/ice_sbq_cmd.h | 5 +-\n 4 files changed, 402 insertions(+), 3 deletions(-)\n create mode 100644 drivers/net/ethernet/intel/ice/ice_cpi.c\n create mode 100644 drivers/net/ethernet/intel/ice/ice_cpi.h", "diff": "diff --git a/drivers/net/ethernet/intel/ice/Makefile b/drivers/net/ethernet/intel/ice/Makefile\nindex 5b2c666496e7..38db476ab2ec 100644\n--- a/drivers/net/ethernet/intel/ice/Makefile\n+++ b/drivers/net/ethernet/intel/ice/Makefile\n@@ -54,7 +54,7 @@ ice-$(CONFIG_PCI_IOV) +=\t\\\n \tice_vf_mbx.o\t\t\\\n \tice_vf_vsi_vlan_ops.o\t\\\n \tice_vf_lib.o\n-ice-$(CONFIG_PTP_1588_CLOCK) += ice_ptp.o ice_ptp_hw.o ice_dpll.o ice_tspll.o\n+ice-$(CONFIG_PTP_1588_CLOCK) += ice_ptp.o ice_ptp_hw.o ice_dpll.o ice_tspll.o ice_cpi.o\n ice-$(CONFIG_DCB) += ice_dcb.o ice_dcb_nl.o ice_dcb_lib.o\n ice-$(CONFIG_RFS_ACCEL) += ice_arfs.o\n ice-$(CONFIG_XDP_SOCKETS) += ice_xsk.o\ndiff --git a/drivers/net/ethernet/intel/ice/ice_cpi.c b/drivers/net/ethernet/intel/ice/ice_cpi.c\nnew file mode 100644\nindex 000000000000..6be8d8497449\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/ice/ice_cpi.c\n@@ -0,0 +1,337 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/* Copyright (C) 2018-2026 Intel Corporation */\n+\n+#include \"ice_type.h\"\n+#include \"ice_common.h\"\n+#include \"ice_ptp_hw.h\"\n+#include \"ice_cpi.h\"\n+\n+/**\n+ * ice_cpi_get_dest_dev - get destination PHY for given phy index\n+ * @hw: pointer to the HW struct\n+ * @phy: phy index of port the CPI action is taken on\n+ *\n+ * Return: sideband queue destination PHY device.\n+ */\n+static enum ice_sbq_dev_id ice_cpi_get_dest_dev(struct ice_hw *hw, u8 phy)\n+{\n+\tu8 curr_phy = hw->lane_num / hw->ptp.ports_per_phy;\n+\n+\t/* In the driver, lanes 4..7 are in fact 0..3 on a second PHY.\n+\t * On a single complex E825C, PHY 0 is always destination device phy_0\n+\t * and PHY 1 is phy_0_peer.\n+\t * On dual complex E825C, device phy_0 points to PHY on a current\n+\t * complex and phy_0_peer to PHY on a different complex.\n+\t */\n+\tif ((!ice_is_dual(hw) && phy) ||\n+\t (ice_is_dual(hw) && phy != curr_phy))\n+\t\treturn ice_sbq_dev_phy_0_peer;\n+\telse\n+\t\treturn ice_sbq_dev_phy_0;\n+}\n+\n+/**\n+ * ice_cpi_write_phy - Write a CPI port register\n+ * @hw: pointer to the HW struct\n+ * @phy: phy index of port the CPI action is taken on\n+ * @addr: PHY register address\n+ * @val: Value to write\n+ *\n+ * Return:\n+ * * 0 on success\n+ * * other error codes when failed to write to PHY\n+ */\n+static int ice_cpi_write_phy(struct ice_hw *hw, u8 phy, u32 addr, u32 val)\n+{\n+\tstruct ice_sbq_msg_input msg = {\n+\t\t.dest_dev = ice_cpi_get_dest_dev(hw, phy),\n+\t\t.opcode = ice_sbq_msg_wr_np,\n+\t\t.msg_addr_low = lower_16_bits(addr),\n+\t\t.msg_addr_high = upper_16_bits(addr),\n+\t\t.data = val\n+\t};\n+\tint err;\n+\n+\terr = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);\n+\tif (err)\n+\t\tice_debug(hw, ICE_DBG_PTP,\n+\t\t\t \"Failed to write CPI msg to phy %d, err: %d\\n\",\n+\t\t\t phy, err);\n+\n+\treturn err;\n+}\n+\n+/**\n+ * ice_cpi_read_phy - Read a CPI port register\n+ * @hw: pointer to the HW struct\n+ * @phy: phy index of port the CPI action is taken on\n+ * @addr: PHY register address\n+ * @val: storage for register value\n+ *\n+ * Return:\n+ * * 0 on success\n+ * * other error codes when failed to read from PHY\n+ */\n+static int ice_cpi_read_phy(struct ice_hw *hw, u8 phy, u32 addr, u32 *val)\n+{\n+\tstruct ice_sbq_msg_input msg = {\n+\t\t.dest_dev = ice_cpi_get_dest_dev(hw, phy),\n+\t\t.opcode = ice_sbq_msg_rd,\n+\t\t.msg_addr_low = lower_16_bits(addr),\n+\t\t.msg_addr_high = upper_16_bits(addr)\n+\t};\n+\tint err;\n+\n+\terr = ice_sbq_rw_reg(hw, &msg, LIBIE_AQ_FLAG_RD);\n+\tif (err) {\n+\t\tice_debug(hw, ICE_DBG_PTP,\n+\t\t\t \"Failed to read CPI msg from phy %d, err: %d\\n\",\n+\t\t\t phy, err);\n+\t\treturn err;\n+\t}\n+\n+\t*val = msg.data;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ice_cpi_wait_req0_ack0 - waits for CPI interface to be available\n+ * @hw: pointer to the HW struct\n+ * @phy: phy index of port the CPI action is taken on\n+ *\n+ * This function checks if CPI interface is ready to use by CPI client.\n+ * It's done by assuring LM.CMD.REQ and PHY.CMD.ACK bit in CPI\n+ * interface registers to be 0.\n+ *\n+ * Return: 0 on success, negative on error\n+ */\n+static int ice_cpi_wait_req0_ack0(struct ice_hw *hw, int phy)\n+{\n+\tu32 phy_val;\n+\tu32 lm_val;\n+\n+\tfor (int i = 0; i < CPI_RETRIES_COUNT; i++) {\n+\t\tint err;\n+\n+\t\t/* check if another CPI Client is also accessing CPI */\n+\t\terr = ice_cpi_read_phy(hw, phy, CPI0_LM1_CMD_DATA, &lm_val);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t\tif (FIELD_GET(CPI_LM_CMD_REQ_M, lm_val))\n+\t\t\treturn -EBUSY;\n+\n+\t\t/* check if PHY.ACK is deasserted */\n+\t\terr = ice_cpi_read_phy(hw, phy, CPI0_PHY1_CMD_DATA, &phy_val);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t\tif (FIELD_GET(CPI_PHY_CMD_ERROR_M, phy_val))\n+\t\t\treturn -EFAULT;\n+\t\tif (!FIELD_GET(CPI_PHY_CMD_ACK_M, phy_val))\n+\t\t\t/* req0 and ack0 at this point - ready to go */\n+\t\t\treturn 0;\n+\n+\t\tmsleep(CPI_RETRIES_CADENCE_MS);\n+\t}\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+/**\n+ * ice_cpi_wait_ack - Waits for the PHY.ACK bit to be asserted/deasserted\n+ * @hw: pointer to the HW struct\n+ * @phy: phy index of port the CPI action is taken on\n+ * @asserted: desired state of PHY.ACK bit\n+ * @data: pointer to the user data where PHY.data is stored\n+ *\n+ * This function checks if PHY.ACK bit is asserted or deasserted, depending\n+ * on the phase of CPI handshake. If 'asserted' state is required, PHY command\n+ * data is stored in the 'data' storage.\n+ *\n+ * Return: 0 on success, negative on error\n+ */\n+static int ice_cpi_wait_ack(struct ice_hw *hw, u8 phy, bool asserted,\n+\t\t\t u32 *data)\n+{\n+\tu32 phy_val;\n+\n+\tfor (int i = 0; i < CPI_RETRIES_COUNT; i++) {\n+\t\tint err;\n+\n+\t\terr = ice_cpi_read_phy(hw, phy, CPI0_PHY1_CMD_DATA, &phy_val);\n+\t\tif (err)\n+\t\t\treturn err;\n+\t\tif (FIELD_GET(CPI_PHY_CMD_ERROR_M, phy_val))\n+\t\t\treturn -EFAULT;\n+\t\tif (asserted && FIELD_GET(CPI_PHY_CMD_ACK_M, phy_val)) {\n+\t\t\tif (data)\n+\t\t\t\t*data = phy_val;\n+\t\t\treturn 0;\n+\t\t}\n+\t\tif (!asserted && !FIELD_GET(CPI_PHY_CMD_ACK_M, phy_val))\n+\t\t\treturn 0;\n+\n+\t\tmsleep(CPI_RETRIES_CADENCE_MS);\n+\t}\n+\n+\treturn -ETIMEDOUT;\n+}\n+\n+#define ice_cpi_wait_ack0(hw, port) \\\n+\tice_cpi_wait_ack(hw, port, false, NULL)\n+\n+#define ice_cpi_wait_ack1(hw, port, data) \\\n+\tice_cpi_wait_ack(hw, port, true, data)\n+\n+/**\n+ * ice_cpi_req0 - deasserts LM.REQ bit\n+ * @hw: pointer to the HW struct\n+ * @phy: phy index of port the CPI action is taken on\n+ * @data: the command data\n+ *\n+ * Return: 0 on success, negative on CPI write error\n+ */\n+static int ice_cpi_req0(struct ice_hw *hw, u8 phy, u32 data)\n+{\n+\tdata &= ~CPI_LM_CMD_REQ_M;\n+\n+\treturn ice_cpi_write_phy(hw, phy, CPI0_LM1_CMD_DATA, data);\n+}\n+\n+/**\n+ * ice_cpi_exec_cmd - writes command data to CPI interface\n+ * @hw: pointer to the HW struct\n+ * @phy: phy index of port the CPI action is taken on\n+ * @data: the command data\n+ *\n+ * Return: 0 on success, otherwise negative on error\n+ */\n+static int ice_cpi_exec_cmd(struct ice_hw *hw, int phy, u32 data)\n+{\n+\treturn ice_cpi_write_phy(hw, phy, CPI0_LM1_CMD_DATA, data);\n+}\n+\n+/**\n+ * ice_cpi_exec - executes CPI command\n+ * @hw: pointer to the HW struct\n+ * @phy: phy index of port the CPI action is taken on\n+ * @cmd: pointer to the command struct to execute\n+ * @resp: pointer to user allocated CPI response struct\n+ *\n+ * This function executes CPI request with respect to CPI handshake\n+ * mechanism.\n+ *\n+ * Return: 0 on success, otherwise negative on error\n+ */\n+int ice_cpi_exec(struct ice_hw *hw, u8 phy,\n+\t\t const struct ice_cpi_cmd *cmd,\n+\t\t struct ice_cpi_resp *resp)\n+{\n+\tu32 phy_cmd, lm_cmd = 0;\n+\tint err, err1 = 0;\n+\n+\tif (!cmd || !resp)\n+\t\treturn -EINVAL;\n+\n+\tlm_cmd =\n+\t\tFIELD_PREP(CPI_LM_CMD_REQ_M, CPI_LM_CMD_REQ) |\n+\t\tFIELD_PREP(CPI_LM_CMD_GET_SET_M, cmd->set) |\n+\t\tFIELD_PREP(CPI_LM_CMD_OPCODE_M, cmd->opcode) |\n+\t\tFIELD_PREP(CPI_LM_CMD_PORTLANE_M, cmd->port) |\n+\t\tFIELD_PREP(CPI_LM_CMD_DATA_M, cmd->data);\n+\n+\t/* 1. Try to acquire the bus, PHY ACK should be low before we begin */\n+\terr = ice_cpi_wait_req0_ack0(hw, phy);\n+\tif (err)\n+\t\tgoto cpi_exec_exit;\n+\n+\t/* 2. We start the CPI request */\n+\terr = ice_cpi_exec_cmd(hw, phy, lm_cmd);\n+\tif (err)\n+\t\tgoto cpi_exec_exit;\n+\n+\t/*\n+\t * 3. Wait for CPI confirmation, PHY ACK should be asserted and opcode\n+\t * echoed in the response\n+\t */\n+\terr = ice_cpi_wait_ack1(hw, phy, &phy_cmd);\n+\tif (err)\n+\t\tgoto cpi_deassert;\n+\n+\tif (FIELD_GET(CPI_PHY_CMD_ACK_M, phy_cmd) &&\n+\t FIELD_GET(CPI_LM_CMD_OPCODE_M, lm_cmd) !=\n+\t FIELD_GET(CPI_PHY_CMD_OPCODE_M, phy_cmd)) {\n+\t\terr = -EFAULT;\n+\t\tgoto cpi_deassert;\n+\t}\n+\n+\tresp->opcode = FIELD_GET(CPI_PHY_CMD_OPCODE_M, phy_cmd);\n+\tresp->data = FIELD_GET(CPI_PHY_CMD_DATA_M, phy_cmd);\n+\tresp->port = FIELD_GET(CPI_PHY_CMD_PORTLANE_M, phy_cmd);\n+\n+cpi_deassert:\n+\t/* 4. We deassert REQ */\n+\terr1 = ice_cpi_req0(hw, phy, lm_cmd);\n+\tif (err1)\n+\t\tgoto cpi_exec_exit;\n+\n+\t/* 5. PHY ACK should be deasserted in response */\n+\terr1 = ice_cpi_wait_ack0(hw, phy);\n+\n+cpi_exec_exit:\n+\tif (!err)\n+\t\terr = err1;\n+\n+\treturn err;\n+}\n+\n+/**\n+ * ice_cpi_set_cmd - execute CPI SET command\n+ * @hw: pointer to the HW struct\n+ * @opcode: CPI command opcode\n+ * @phy: phy index CPI command is applied for\n+ * @port_lane: ephy index CPI command is applied for\n+ * @data: CPI opcode context specific data\n+ *\n+ * Return: 0 on success.\n+ */\n+static int ice_cpi_set_cmd(struct ice_hw *hw, u16 opcode, u8 phy, u8 port_lane,\n+\t\t\t u16 data)\n+{\n+\tstruct ice_cpi_resp cpi_resp = {0};\n+\tstruct ice_cpi_cmd cpi_cmd = {\n+\t\t.opcode = opcode,\n+\t\t.set = true,\n+\t\t.port = port_lane,\n+\t\t.data = data,\n+\t};\n+\n+\treturn ice_cpi_exec(hw, phy, &cpi_cmd, &cpi_resp);\n+}\n+\n+/**\n+ * ice_cpi_ena_dis_clk_ref - enables/disables Tx reference clock on port\n+ * @hw: pointer to the HW struct\n+ * @phy: phy index of port for which Tx reference clock is enabled/disabled\n+ * @clk: Tx reference clock to enable or disable\n+ * @enable: bool value to enable or disable Tx reference clock\n+ *\n+ * This function executes CPI request to enable or disable specific\n+ * Tx reference clock on given PHY.\n+ *\n+ * Return: 0 on success.\n+ */\n+int ice_cpi_ena_dis_clk_ref(struct ice_hw *hw, u8 phy,\n+\t\t\t enum ice_e825c_ref_clk clk, bool enable)\n+{\n+\tu16 val;\n+\n+\tval = FIELD_PREP(CPI_OPCODE_PHY_CLK_PHY_SEL_M, phy) |\n+\t FIELD_PREP(CPI_OPCODE_PHY_CLK_REF_CTRL_M,\n+\t\t\t enable ? CPI_OPCODE_PHY_CLK_ENABLE :\n+\t\t\t CPI_OPCODE_PHY_CLK_DISABLE) |\n+\t FIELD_PREP(CPI_OPCODE_PHY_CLK_REF_SEL_M, clk);\n+\n+\treturn ice_cpi_set_cmd(hw, CPI_OPCODE_PHY_CLK, phy, 0, val);\n+}\n+\ndiff --git a/drivers/net/ethernet/intel/ice/ice_cpi.h b/drivers/net/ethernet/intel/ice/ice_cpi.h\nnew file mode 100644\nindex 000000000000..932fe0c0824a\n--- /dev/null\n+++ b/drivers/net/ethernet/intel/ice/ice_cpi.h\n@@ -0,0 +1,61 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/* Copyright (C) 2018-2025 Intel Corporation */\n+\n+#ifndef _ICE_CPI_H_\n+#define _ICE_CPI_H_\n+\n+#define CPI0_PHY1_CMD_DATA\t0x7FD028\n+#define CPI0_LM1_CMD_DATA\t0x7FD024\n+#define CPI_RETRIES_COUNT\t10\n+#define CPI_RETRIES_CADENCE_MS\t100\n+\n+/* CPI PHY CMD DATA register (CPI0_PHY1_CMD_DATA) */\n+#define CPI_PHY_CMD_DATA_M\tGENMASK(15, 0)\n+#define CPI_PHY_CMD_OPCODE_M\tGENMASK(23, 16)\n+#define CPI_PHY_CMD_PORTLANE_M\tGENMASK(26, 24)\n+#define CPI_PHY_CMD_RSVD_M\tGENMASK(29, 27)\n+#define CPI_PHY_CMD_ERROR_M\tBIT(30)\n+#define CPI_PHY_CMD_ACK_M\tBIT(31)\n+\n+/* CPI LM CMD DATA register (CPI0_LM1_CMD_DATA) */\n+#define CPI_LM_CMD_DATA_M\tGENMASK(15, 0)\n+#define CPI_LM_CMD_OPCODE_M\tGENMASK(23, 16)\n+#define CPI_LM_CMD_PORTLANE_M\tGENMASK(26, 24)\n+#define CPI_LM_CMD_RSVD_M\tGENMASK(28, 27)\n+#define CPI_LM_CMD_GET_SET_M\tBIT(29)\n+#define CPI_LM_CMD_RESET_M\tBIT(30)\n+#define CPI_LM_CMD_REQ_M BIT(31)\n+\n+#define CPI_OPCODE_PHY_CLK\t\t\t0xF1\n+#define CPI_OPCODE_PHY_CLK_PHY_SEL_M\t\tGENMASK(9, 6)\n+#define CPI_OPCODE_PHY_CLK_REF_CTRL_M\t\tGENMASK(5, 4)\n+#define CPI_OPCODE_PHY_CLK_PORT_SEL\t\t0\n+#define CPI_OPCODE_PHY_CLK_DISABLE\t\t1\n+#define CPI_OPCODE_PHY_CLK_ENABLE\t\t2\n+#define CPI_OPCODE_PHY_CLK_REF_SEL_M\t\tGENMASK(3, 0)\n+\n+#define CPI_OPCODE_PHY_PCS_RESET\t\t0xF0\n+#define CPI_OPCODE_PHY_PCS_ONPI_RESET_VAL\t0x3F\n+\n+#define CPI_LM_CMD_REQ\t\t1\n+#define CPI_LM_CMD_SET\t\t1\n+\n+struct ice_cpi_cmd {\n+\tu8 port;\n+\tu8 opcode;\n+\tu16 data;\n+\tbool set;\n+};\n+\n+struct ice_cpi_resp {\n+\tu8 port;\n+\tu8 opcode;\n+\tu16 data;\n+};\n+\n+int ice_cpi_exec(struct ice_hw *hw, u8 phy,\n+\t\t const struct ice_cpi_cmd *cmd,\n+\t\t struct ice_cpi_resp *resp);\n+int ice_cpi_ena_dis_clk_ref(struct ice_hw *hw, u8 port,\n+\t\t\t enum ice_e825c_ref_clk clk, bool enable);\n+#endif /* _ICE_CPI_H_ */\ndiff --git a/drivers/net/ethernet/intel/ice/ice_sbq_cmd.h b/drivers/net/ethernet/intel/ice/ice_sbq_cmd.h\nindex 21bb861febbf..226243d32968 100644\n--- a/drivers/net/ethernet/intel/ice/ice_sbq_cmd.h\n+++ b/drivers/net/ethernet/intel/ice/ice_sbq_cmd.h\n@@ -54,8 +54,9 @@ enum ice_sbq_dev_id {\n };\n \n enum ice_sbq_msg_opcode {\n-\tice_sbq_msg_rd\t= 0x00,\n-\tice_sbq_msg_wr\t= 0x01\n+\tice_sbq_msg_rd\t\t= 0x00,\n+\tice_sbq_msg_wr\t\t= 0x01,\n+\tice_sbq_msg_wr_np\t= 0x02\n };\n \n #define ICE_SBQ_MSG_FLAGS\t0x40\n", "prefixes": [ "v5", "net-next", "6/8" ] }