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GET /api/1.0/patches/2219350/?format=api
{ "id": 2219350, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2219350/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260402215629.745866-30-ruslichenko.r@gmail.com>", "date": "2026-04-02T21:56:14", "name": "[v3,29/33] hw/intc/arm_gicv3: Implement FDTGenericIntc interface", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6a8b95f8896028577944d7525f0d17c83734311a", "submitter": { "id": 92275, "url": "http://patchwork.ozlabs.org/api/1.0/people/92275/?format=api", "name": "Ruslan Ruslichenko", "email": "ruslichenko.r@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260402215629.745866-30-ruslichenko.r@gmail.com/mbox/", "series": [ { "id": 498555, "url": "http://patchwork.ozlabs.org/api/1.0/series/498555/?format=api", "date": "2026-04-02T21:55:47", "name": "hw/arm: Introduce generic FDT-driven machine", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/498555/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219350/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=rMkHPGi7;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmwkD4Brfz1yD3\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 03 Apr 2026 08:59:32 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w8Q3C-0001KX-Ez; Thu, 02 Apr 2026 17:58:06 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <ruslichenko.r@gmail.com>)\n id 1w8Q2k-0000Hb-Fr\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 17:57:39 -0400", "from mail-ej1-x632.google.com ([2a00:1450:4864:20::632])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <ruslichenko.r@gmail.com>)\n id 1w8Q2h-0007Gk-0L\n for qemu-devel@nongnu.org; Thu, 02 Apr 2026 17:57:37 -0400", "by mail-ej1-x632.google.com with SMTP id\n a640c23a62f3a-b9c11eba219so168204466b.2\n for <qemu-devel@nongnu.org>; Thu, 02 Apr 2026 14:57:34 -0700 (PDT)", "from thinkpad-t470s.. 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Iglesias\" <edgar.iglesias@gmail.com>,\n Ruslan_Ruslichenko@epam.com, balaton@eik.bme.hu", "Subject": "[PATCH v3 29/33] hw/intc/arm_gicv3: Implement FDTGenericIntc\n interface", "Date": "Thu, 2 Apr 2026 23:56:14 +0200", "Message-ID": "<20260402215629.745866-30-ruslichenko.r@gmail.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260402215629.745866-1-ruslichenko.r@gmail.com>", "References": "<20260402215629.745866-1-ruslichenko.r@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::632;\n envelope-from=ruslichenko.r@gmail.com; helo=mail-ej1-x632.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Ruslan Ruslichenko <Ruslan_Ruslichenko@epam.com>\n\nThis patch implements the FDTGenericIntc interface for the\nARM GICv3 interrupt controller.\n\nThis enables the generic FDT machine infrastructure to\nautomatically wire up the GIC and resolve interrupts\ndefined in the Device Tree.\n\nSigned-off-by: Ruslan Ruslichenko <Ruslan_Ruslichenko@epam.com>\n---\n hw/intc/arm_gicv3.c | 45 +++++++++++++++++++++++++\n hw/intc/arm_gicv3_common.c | 68 ++++++++++++++++++++++++++++++++++++++\n 2 files changed, 113 insertions(+)", "diff": "diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c\nindex 542f81ea49..e7e98ef9a5 100644\n--- a/hw/intc/arm_gicv3.c\n+++ b/hw/intc/arm_gicv3.c\n@@ -18,9 +18,13 @@\n #include \"qemu/osdep.h\"\n #include \"qapi/error.h\"\n #include \"qemu/module.h\"\n+#include \"hw/core/cpu.h\"\n+#include \"hw/core/boards.h\"\n #include \"hw/intc/arm_gicv3.h\"\n #include \"gicv3_internal.h\"\n \n+#include \"hw/core/fdt_generic_util.h\"\n+\n static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio, bool nmi)\n {\n /* Return true if this IRQ at this priority should take\n@@ -452,14 +456,55 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)\n gicv3_init_cpuif(s);\n }\n \n+static void arm_gic_fdt_auto_parent(FDTGenericIntc *obj, Error **errp)\n+{\n+ GICv3State *s = ARM_GICV3(obj);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);\n+ int num_cpus = s->num_cpu;\n+ CPUState *cs;\n+ int i = 0;\n+\n+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {\n+ if (i >= s->num_cpu) {\n+ break;\n+ }\n+\n+ sysbus_connect_irq(sbd, i,\n+ qdev_get_gpio_in(DEVICE(cs), 0));\n+ sysbus_connect_irq(sbd, i + num_cpus,\n+ qdev_get_gpio_in(DEVICE(cs), 1));\n+ sysbus_connect_irq(sbd, i + 2 * num_cpus,\n+ qdev_get_gpio_in(DEVICE(cs), 2));\n+ sysbus_connect_irq(sbd, i + 3 * num_cpus,\n+ qdev_get_gpio_in(DEVICE(cs), 3));\n+ sysbus_connect_irq(sbd, i + 4 * num_cpus,\n+ qdev_get_gpio_in(DEVICE(cs), 4));\n+ sysbus_connect_irq(sbd, i + 5 * num_cpus,\n+ qdev_get_gpio_in(DEVICE(cs), 5));\n+\n+ if (s->maint_irq) {\n+ int intbase = s->num_irq - GIC_INTERNAL + i * GIC_INTERNAL;\n+ qemu_irq irq = qdev_get_gpio_in(DEVICE(sbd),\n+ intbase + s->maint_irq);\n+ qdev_connect_gpio_out_named(DEVICE(cs),\n+ \"gicv3-maintenance-interrupt\",\n+ 0, irq);\n+ }\n+\n+ i++;\n+ }\n+}\n+\n static void arm_gicv3_class_init(ObjectClass *klass, const void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(klass);\n ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);\n ARMGICv3Class *agc = ARM_GICV3_CLASS(klass);\n+ FDTGenericIntcClass *fgic = FDT_GENERIC_INTC_CLASS(klass);\n \n agcc->post_load = arm_gicv3_post_load;\n device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize);\n+ fgic->auto_parent = arm_gic_fdt_auto_parent;\n }\n \n static const TypeInfo arm_gicv3_info = {\ndiff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c\nindex 9200671c7a..a393540825 100644\n--- a/hw/intc/arm_gicv3_common.c\n+++ b/hw/intc/arm_gicv3_common.c\n@@ -34,6 +34,7 @@\n #include \"system/kvm.h\"\n #include \"system/whpx.h\"\n \n+#include \"hw/core/fdt_generic_util.h\"\n \n static void gicv3_gicd_no_migration_shift_bug_post_load(GICv3State *cs)\n {\n@@ -367,6 +368,69 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,\n }\n }\n \n+#define FDT_GENERIC_GICV3_TYPE_AFFINITY_ALL 0x01000000U\n+#define FDT_GENERIC_GICV3_TYPE_AFFINITY_IDX 0x02000000U\n+\n+static int arm_gicv3_common_fdt_get_irq(FDTGenericIntc *obj, qemu_irq *irqs,\n+ uint32_t *cells, int ncells, int max,\n+ Error **errp)\n+{\n+ GICv3State *gs = ARM_GICV3_COMMON(obj);\n+ int cpu = 0;\n+ uint32_t qemu_type;\n+ uint32_t cpu_mask;\n+ uint32_t idx;\n+\n+ if (ncells != 3) {\n+ error_setg(errp, \"ARM GIC requires 3 interrupt cells, %d cells given\",\n+ ncells);\n+ return 0;\n+ }\n+ idx = cells[1];\n+ qemu_type = cells[0] & 0xff000000;\n+\n+ switch (cells[0] & 0x00ffffff) {\n+ case 0:\n+ if (idx >= gs->num_irq) {\n+ error_setg(errp, \"ARM GIC SPI has maximum index of %\" PRId32 \", \"\n+ \"index %\" PRId32 \" given\", gs->num_irq - 1, idx);\n+ return 0;\n+ }\n+ (*irqs) = qdev_get_gpio_in(DEVICE(obj), cells[1]);\n+ return 1;\n+ case 1: /* PPI */\n+ if (idx >= 16) {\n+ error_setg(errp, \"ARM GIC PPI has maximum index of 15, \"\n+ \"index %\" PRId32 \" given\", idx);\n+ return 0;\n+ }\n+ if (qemu_type == FDT_GENERIC_GICV3_TYPE_AFFINITY_IDX) {\n+ cpu = cells[2] >> 8;\n+ *irqs = qdev_get_gpio_in(DEVICE(obj),\n+ gs->num_irq - 16 + idx + cpu * 32);\n+ return cpu;\n+ }\n+\n+ cpu_mask = cells[2] >> 8;\n+ while ((cpu_mask || qemu_type == FDT_GENERIC_GICV3_TYPE_AFFINITY_ALL)\n+ && cpu < max && cpu < gs->num_cpu) {\n+ if ((cpu_mask & 1) ||\n+ qemu_type == FDT_GENERIC_GICV3_TYPE_AFFINITY_ALL) {\n+ *irqs = qdev_get_gpio_in(DEVICE(obj),\n+ gs->num_irq - 16 + idx + cpu * 32);\n+ irqs++;\n+ }\n+ cpu_mask >>= 1;\n+ cpu++;\n+ }\n+ return cpu;\n+ default:\n+ error_setg(errp, \"Invalid cell 0 value in interrupt binding: %d\",\n+ cells[0]);\n+ return 0;\n+ }\n+}\n+\n static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)\n {\n GICv3State *s = ARM_GICV3_COMMON(dev);\n@@ -624,12 +688,15 @@ static void arm_gicv3_common_class_init(ObjectClass *klass, const void *data)\n DeviceClass *dc = DEVICE_CLASS(klass);\n ResettableClass *rc = RESETTABLE_CLASS(klass);\n ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);\n+ FDTGenericIntcClass *fgic = FDT_GENERIC_INTC_CLASS(klass);\n+\n \n rc->phases.hold = arm_gicv3_common_reset_hold;\n dc->realize = arm_gicv3_common_realize;\n device_class_set_props(dc, arm_gicv3_common_properties);\n dc->vmsd = &vmstate_gicv3;\n albifc->arm_linux_init = arm_gic_common_linux_init;\n+ fgic->get_irq = arm_gicv3_common_fdt_get_irq;\n }\n \n static const TypeInfo arm_gicv3_common_type = {\n@@ -641,6 +708,7 @@ static const TypeInfo arm_gicv3_common_type = {\n .abstract = true,\n .interfaces = (const InterfaceInfo[]) {\n { TYPE_ARM_LINUX_BOOT_IF },\n+ { TYPE_FDT_GENERIC_INTC },\n { },\n },\n };\n", "prefixes": [ "v3", "29/33" ] }