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GET /api/1.0/patches/2219185/?format=api
{ "id": 2219185, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2219185/?format=api", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.0/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260402-tegra264-pcie-v4-1-21e2e19987e8@nvidia.com>", "date": "2026-04-02T14:27:35", "name": "[v4,1/4] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "edf80403b512f86b3bdb7714d8e77ebfaecbafb7", "submitter": { "id": 92481, "url": "http://patchwork.ozlabs.org/api/1.0/people/92481/?format=api", "name": "Thierry Reding", "email": "thierry.reding@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260402-tegra264-pcie-v4-1-21e2e19987e8@nvidia.com/mbox/", "series": [ { "id": 498493, "url": "http://patchwork.ozlabs.org/api/1.0/series/498493/?format=api", "date": "2026-04-02T14:27:35", "name": "PCI: tegra: Add Tegra264 support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/498493/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2219185/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-13536-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=Np8hZNYt;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1775140078; cv=none;\n b=cmHS8w9gdAUbOKP9+ZKnWhV2zPHtpWKMplYzK0PMQChgPd8qsjJo2/ZNgqz3GtbB4RDbpfJq4hxaeN6uo1R1d0iRkE2iQYXKLS18s07m+2KlxDaxfGZh9ccwniBilcXbFmB6Go5yHgfbMImitHwainzz0BVIu0/rJafVXVzBeUc=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1775140078; c=relaxed/simple;\n\tbh=NAByKfU/ZjEewVQnAkmCy1V2fy4PZYtDqNWOg10g8F4=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=MTyzwIwbyJqx3IBqVZ/eGENR2q3GmQ6MKirba2LFd8/iMZp3NjqemLST2LEg2OI04UcrPRBDTVwJUYFqTdgxP/YBd5DnCZT8WYVt3q3Ou9YYqoLStHGhrcsXsU9mlM3PoVFJx93jxlJGphFbf0lw0jWNlIBqYkrzsphSW9oIDkY=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=Np8hZNYt; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1775140077;\n\tbh=NAByKfU/ZjEewVQnAkmCy1V2fy4PZYtDqNWOg10g8F4=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:From;\n\tb=Np8hZNYtGt5gbuN6MvaRAeCqJ3F1oqjeR011UgZKWdilMm1NWwEoLJsrop9vEKEKJ\n\t CayjbD65CgAq6kxmTN8/ZMRp6UbYRXHlvyQOrz43iT1i9DhBkbE6llfzKbHqVGbHqF\n\t dsl60/acNLsak+orkqezhAvI3XmmvonG/75gxEvZG1O2auyx6FUxOJM7Vty8iOE2kI\n\t +21b6K4dPmLpZGAKuwA2BVZ0XHXDUr6qAf6eXd18c8zJtGEZocRpqAI+pDz1Wpvh4w\n\t Ank1UlBk7SRIQT8kGQQsNqqE0Z42e2gjIlq4NqcgLJQkmzABy5cDqtHaNKQxYaML1Q\n\t 7ur41gY0vsfyQ==", "From": "Thierry Reding <thierry.reding@kernel.org>", "Date": "Thu, 02 Apr 2026 16:27:35 +0200", "Subject": "[PATCH v4 1/4] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe\n controller", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260402-tegra264-pcie-v4-1-21e2e19987e8@nvidia.com>", "References": "<20260402-tegra264-pcie-v4-0-21e2e19987e8@nvidia.com>", "In-Reply-To": "<20260402-tegra264-pcie-v4-0-21e2e19987e8@nvidia.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy?=\n\t=?utf-8?q?=C5=84ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Thierry Reding <thierry.reding@gmail.com>,\n Jonathan Hunter <jonathanh@nvidia.com>,\n Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>,\n Hou Zhiqiang <Zhiqiang.Hou@nxp.com>,\n Thomas Petazzoni <thomas.petazzoni@bootlin.com>,\n =?utf-8?q?Pali_Roh=C3=A1r?= <pali@kernel.org>,\n Michal Simek <michal.simek@amd.com>, Kevin Xie <kevin.xie@starfivetech.com>", "Cc": "linux-pci@vger.kernel.org, devicetree@vger.kernel.org,\n linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-arm-kernel@lists.infradead.org, Thierry Reding <treding@nvidia.com>", "X-Mailer": "b4 0.15.1", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=6863; i=treding@nvidia.com;\n h=from:subject:message-id; bh=OWl+kwHniIJmn2xT8tkW6mFB/fgovQVw1CKdkoUXhPs=;\n b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBpznznvY0VyUIk/fnSv3MCEw9J6m6PLKgotKsZu\n ORvzT4pPzeJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCac585wAKCRDdI6zXfz6z\n oTzCD/0V1hNnSNbAiKMSLVeNsPoLZy4RnVdQ7bR1WzYlNd042sabyfuzOnLelO99DMyrlbVoNge\n YdmBgNaAuoBJCQcTUxkKLp7IIiNNQlBAxxUNCnnfutVal7IKePDgcf2ZiclzO7Urlyi7tuL+GEB\n jBf6gAP8758J9KRcy7IUTSIsbeicTMhafg5Rvg5YaIISl6oAzNj99creo068Ke43pd+hc5ArT8Z\n GZGpql1IiB5exxe2Y5dsjMKF7kE+ZRiqiNDwFwTc+CenCx/yXUtw6WNvTgXDHF6qbvTzKHAk7G4\n tgYDg7JH7+Tvp8Ii2y5A7hc1EKBNvizKuCTtOoX1RcXn2CXBn/+gWIA+N6zB78liX0Vi9GcWvbn\n 9J0NtyC7yyyKnR2pJTdRI2eRBSJAazoGEZv5MtFp8D5s2G56CeUKHw6Nqp9C8W5ntGu5TTM1Sqe\n nhbvFbFHE8cLwJ5AFyVlGv874nEYCpsZbdNwCLfJd4wRUJzDYxbFrlGq8kBRHaTi4xwHiZDBO5G\n S5pM1aYKbrKG6V8SsDuVhPWIGSApZHau1ecXEjmiDCp2lcb6wBAikX0XOMVDpwq7Rv4kJmsgLDA\n k71lZkvIfSmXawWjf72LlCjpsznvyeA/K3ux9QNVqFxvbxm+JxGnlGjJoLhnnb+SsEWB8Q1uo20\n tv/SMhE1jXe5wwg==", "X-Developer-Key": "i=treding@nvidia.com; a=openpgp;\n fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nThe six PCIe controllers found on Tegra264 are of two types: one is used\nfor the internal GPU and therefore is not connected to a UPHY and the\nremaining five controllers are typically routed to a PCI slot and have\nadditional controls for the physical link.\n\nWhile these controllers can be switched into endpoint mode, this binding\ndescribes the root complex mode only.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\nChanges in v4:\n- ECAM is outside of the controller's region, so it cannot be the first\n reg entry, otherwise we get warnings because it doesn't match the\n unit-address, so revert back to oneOf construct\n\nChanges in v2:\n- move ECAM region first and unify C0 vs. C1-C5\n- move unevaluatedProperties to right before the examples\n- add description to clarify the two types of controllers\n- add examples for C0 and C1-C5\n---\n .../bindings/pci/nvidia,tegra264-pcie.yaml | 174 +++++++++++++++++++++\n 1 file changed, 174 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml\nnew file mode 100644\nindex 000000000000..acb677d477fb\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml\n@@ -0,0 +1,174 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: NVIDIA Tegra264 PCIe controller\n+\n+maintainers:\n+ - Thierry Reding <thierry.reding@gmail.com>\n+ - Jon Hunter <jonathanh@nvidia.com>\n+\n+description: |\n+ Of the six PCIe controllers found on Tegra264, one (C0) is used for the\n+ internal GPU and the other five (C1-C5) are routed to connectors such as\n+ PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1\n+ through C5, but not for C0.\n+\n+properties:\n+ compatible:\n+ const: nvidia,tegra264-pcie\n+\n+ reg:\n+ minItems: 4\n+ maxItems: 5\n+\n+ reg-names:\n+ minItems: 4\n+ maxItems: 5\n+\n+ interrupts:\n+ minItems: 1\n+ maxItems: 4\n+\n+ dma-coherent: true\n+\n+ nvidia,bpmp:\n+ $ref: /schemas/types.yaml#/definitions/phandle-array\n+ description: |\n+ Must contain a pair of phandle (to the BPMP controller node) and\n+ controller ID. The following are the controller IDs for each controller:\n+\n+ 0: C0\n+ 1: C1\n+ 2: C2\n+ 3: C3\n+ 4: C4\n+ 5: C5\n+ items:\n+ - items:\n+ - description: phandle to the BPMP controller node\n+ - description: PCIe controller ID\n+ maximum: 5\n+\n+required:\n+ - interrupt-map\n+ - interrupt-map-mask\n+ - iommu-map\n+ - msi-map\n+ - nvidia,bpmp\n+\n+allOf:\n+ - $ref: /schemas/pci/pci-host-bridge.yaml#\n+ - oneOf:\n+ - description: C0 controller (no UPHY)\n+ properties:\n+ reg:\n+ items:\n+ - description: application layer registers\n+ - description: transaction layer registers\n+ - description: privileged transaction layer registers\n+ - description: ECAM compatible configuration space\n+\n+ reg-names:\n+ items:\n+ - const: xal\n+ - const: xtl\n+ - const: xtl-pri\n+ - const: ecam\n+\n+ - description: C1-C5 controllers (with UPHY)\n+ properties:\n+ reg:\n+ items:\n+ - description: application layer registers\n+ - description: transaction layer registers\n+ - description: privileged transaction layer registers\n+ - description: data link/physical layer registers\n+ - description: ECAM compatible configuration space\n+\n+ reg-names:\n+ items:\n+ - const: xal\n+ - const: xtl\n+ - const: xtl-pri\n+ - const: xpl\n+ - const: ecam\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ bus {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pci@c000000 {\n+ compatible = \"nvidia,tegra264-pcie\";\n+ reg = <0x00 0x0c000000 0x0 0x00004000>,\n+ <0x00 0x0c004000 0x0 0x00001000>,\n+ <0x00 0x0c005000 0x0 0x00001000>,\n+ <0xd0 0xb0000000 0x0 0x10000000>;\n+ reg-names = \"xal\", \"xtl\", \"xtl-pri\", \"ecam\";\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ device_type = \"pci\";\n+ linux,pci-domain = <0x00>;\n+ #interrupt-cells = <0x1>;\n+\n+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 4>,\n+ <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 4>,\n+ <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 4>,\n+ <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 4>;\n+\n+ iommu-map = <0x0 &smmu2 0x10000 0x10000>;\n+ msi-map = <0x0 &its 0x210000 0x10000>;\n+ dma-coherent;\n+\n+ ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>,\n+ <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>,\n+ <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>;\n+ bus-range = <0x0 0xff>;\n+\n+ nvidia,bpmp = <&bpmp 0>;\n+ };\n+ };\n+\n+ - |\n+ bus {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pci@8400000 {\n+ compatible = \"nvidia,tegra264-pcie\";\n+ reg = <0x00 0x08400000 0x0 0x00004000>,\n+ <0x00 0x08404000 0x0 0x00001000>,\n+ <0x00 0x08405000 0x0 0x00001000>,\n+ <0x00 0x08410000 0x0 0x00010000>,\n+ <0xa8 0xb0000000 0x0 0x10000000>;\n+ reg-names = \"xal\", \"xtl\", \"xtl-pri\", \"xpl\", \"ecam\";\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ device_type = \"pci\";\n+ linux,pci-domain = <0x01>;\n+ #interrupt-cells = <1>;\n+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 4>,\n+ <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 4>,\n+ <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 4>,\n+ <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 4>;\n+\n+ iommu-map = <0x0 &smmu1 0x10000 0x10000>;\n+ msi-map = <0x0 &its 0x110000 0x10000>;\n+ dma-coherent;\n+\n+ ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>,\n+ <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>,\n+ <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>;\n+ bus-range = <0x00 0xff>;\n+\n+ nvidia,bpmp = <&bpmp 1>;\n+ };\n+ };\n", "prefixes": [ "v4", "1/4" ] }