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GET /api/1.0/patches/2218697/?format=api
{ "id": 2218697, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2218697/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260401170454.32045-4-yodel.eldar@yodel.dev>", "date": "2026-04-01T17:04:53", "name": "[RFC,3/4] alpha: Replace helper_set_alarm with Typhoon Cchip MMIO register", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "867f770a7ed253307c33478bbe3974d2c6790491", "submitter": { "id": 92094, "url": "http://patchwork.ozlabs.org/api/1.0/people/92094/?format=api", "name": "Yodel Eldar", "email": "yodel.eldar@yodel.dev" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260401170454.32045-4-yodel.eldar@yodel.dev/mbox/", "series": [ { "id": 498370, "url": "http://patchwork.ozlabs.org/api/1.0/series/498370/?format=api", "date": "2026-04-01T17:04:50", "name": "alpha: Decouple the CPU and Typhoon", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/498370/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2218697/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=yodel.dev header.i=@yodel.dev header.a=rsa-sha256\n header.s=rsa2048 header.b=bu8sEM1Q;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fmBGH550Fz1yCp\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 02 Apr 2026 04:06:15 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w7z0X-00016m-Ez; Wed, 01 Apr 2026 13:05:33 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1)\n (envelope-from <bounce+0e9322.97607e-qemu-devel=nongnu.org@yodel.dev>)\n id 1w7z09-0000pl-O6\n for qemu-devel@nongnu.org; Wed, 01 Apr 2026 13:05:11 -0400", "from v512.v5f06b487.use4.send.mailgun.net ([143.55.232.12])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1)\n (envelope-from <bounce+0e9322.97607e-qemu-devel=nongnu.org@yodel.dev>)\n id 1w7z07-00084g-AK\n for qemu-devel@nongnu.org; Wed, 01 Apr 2026 13:05:09 -0400", "from mail.yodel.dev (mail.yodel.dev [35.209.39.246]) by\n aaac95d988df8a5b7476f90d482c0863d3bd26acbd0c843086e3698f5097df11 with SMTP id\n 69cd503bbf9bc69ede7f1800; Wed, 01 Apr 2026 17:04:59 GMT" ], "X-Mailgun-Sid": "WyI4ZDFlNiIsInFlbXUtZGV2ZWxAbm9uZ251Lm9yZyIsIjk3NjA3ZSJd", "X-Mailgun-Sending-Ip": "143.55.232.12", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=yodel.dev;\n s=rsa2048; t=1775063098;\n bh=Ft8NudYzcwgnb/NtMZjokqHSpfT16xJAGl989G7s3EU=;\n h=X-Mailgun-Dkim:From:To:Cc:Subject:Date:Message-ID:In-Reply-To:\n References:MIME-Version:Content-Type:Content-Transfer-Encoding:\n From:Reply-to:Subject:Date:Message-id:To:Cc:Mime-version:\n Content-type:Content-transfer-encoding:In-reply-to:References;\n b=bu8sEM1QanOabgLcZus8CskaneuZFKkKKJyWZpUpwsBaiPu9KvzsE4SQ6UURokgiy\n MdQouLAGskimFVrMpIDNleuP0qvyLhr28ybrDF9C8XKvkup8nM0j85bAf64fWEV2eU\n eF/ou5PlQjraGvy3zhDTONXb7uDdIDEAJl0iX5cyfL2T8gdYG9CvKpFB6nDpnHogdW\n sX1AggpTucEpprgQK1CDXUNNs6jrbypvN0OMj6AaaoidBScYgH351wNIwIAwENkWca\n v9EFnRYzJUeemCoB9C6xAawqVs+y8G9w0jdb7uxdk3iFZnnUbKZIeAtk7kqyXo28kG\n 0KXwWEQihgtpA==", "X-Mailgun-Dkim": [ "no", "no" ], "From": "\"Yodel Eldar\" <yodel.eldar@yodel.dev>", "To": "qemu-devel@nongnu.org", "Cc": "Richard Henderson <richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mat?=\n\t=?utf-8?q?hieu-Daud=C3=A9?= <philmd@linaro.org>,\n Yodel Eldar <yodel.eldar@yodel.dev>", "Subject": "[RFC PATCH 3/4] alpha: Replace helper_set_alarm with Typhoon Cchip\n MMIO register", "Date": "Wed, 1 Apr 2026 12:04:53 -0500", "Message-ID": "<20260401170454.32045-4-yodel.eldar@yodel.dev>", "In-Reply-To": "<20260401170454.32045-1-yodel.eldar@yodel.dev>", "References": "<20260401170454.32045-1-yodel.eldar@yodel.dev>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=143.55.232.12;\n envelope-from=bounce+0e9322.97607e-qemu-devel=nongnu.org@yodel.dev;\n helo=v512.v5f06b487.use4.send.mailgun.net", "X-Spam_score_int": "0", "X-Spam_score": "-0.1", "X-Spam_bar": "/", "X-Spam_report": "(-0.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n HELO_STATIC_HOST=-0.001, RCVD_IN_MSPIKE_H2=-0.01,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=1, RCVD_IN_VALIDITY_RPBL_BLOCKED=1,\n SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Yodel Eldar <yodel.eldar@yodel.dev>\n\nThis commit creates a QEMU-specific (non-standard) MMIO register\nin Typhoon's Cchip to replace helper_set_alarm() and to move\nthe QEMUTimer pointer, alarm_timer, out of the Alpha CPU and into\nthe chipset code.\n\nCurrently, PALcode writes to the QEMU-specific, synthetic\nProcessor Register (index 251) and triggers the invocation of\nhelper_set_alarm() as a side effect in QEMU, thereby setting\nthe timer alarm expiration value.\n\nThis works, because the AlphaCPU contains the QEMUTimer and\nCPUAlphaState stores the alarm expiration value; however, the timer\nalarm callback resides in and is specific to the Typhoon chipset,\nthus the CPU and the chipset are entangled.\n\nBy designating the currently unused offset (0x7c0) of Cchip as the\nlocation of the timer alarm expiration, we can disentangle and\nbetter encapsulate both.\n\nSuggested-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nSigned-off-by: Yodel Eldar <yodel.eldar@yodel.dev>\n---\n\nNotes:\n The patch to the palcode-clipper binary that follows this\n one is necessary for this patch to work; I've left the\n diff to the source in the notes of it for reproduction.\n \n Philippe:\n Thanks, again, for the suggestion of decoupling the CPU from\n the Typhoon using IRQ lines. In my response, I guessed that\n getting the CPU index would be trickier than moving the timer\n into TyphoonState; perhaps you'll find it amusing (as I do)\n that it appears I had that backwards (due to the PALcode\n peculiarity)!\n \n The remaining CPU interrupts will be refactored in v2 of that\n series.\n\n hw/alpha/dp264.c | 4 ++++\n hw/alpha/typhoon.c | 38 ++++++++++++++++++++++++++++++++------\n target/alpha/cpu.c | 17 +++++++++++++++++\n target/alpha/cpu.h | 6 ------\n target/alpha/helper.h | 1 -\n target/alpha/sys_helper.c | 12 ------------\n target/alpha/translate.c | 11 -----------\n 7 files changed, 53 insertions(+), 36 deletions(-)", "diff": "diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c\nindex ce2f8765cd..8e63b48a02 100644\n--- a/hw/alpha/dp264.c\n+++ b/hw/alpha/dp264.c\n@@ -71,6 +71,10 @@ static void clipper_init(MachineState *machine)\n memset(cpus, 0, sizeof(cpus));\n for (i = 0; i < smp_cpus; ++i) {\n cpus[i] = ALPHA_CPU(cpu_create(machine->cpu_type));\n+\n+ qdev_connect_gpio_out_named(DEVICE(typhoon_obj), \"cpu-irq\", i,\n+ qdev_get_gpio_in_named(DEVICE(cpus[i]),\n+ \"timer-irq\", 0));\n }\n \n /*\ndiff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c\nindex 5dadfa7691..a40f690ed1 100644\n--- a/hw/alpha/typhoon.c\n+++ b/hw/alpha/typhoon.c\n@@ -26,6 +26,9 @@ typedef struct TyphoonCchip {\n uint64_t dim[4];\n uint32_t iic[4];\n AlphaCPU *cpu[4];\n+ qemu_irq cpu_irq[4];\n+ QEMUTimer *alarm_timer[4];\n+ uint64_t alarm_expire[4];\n } TyphoonCchip;\n \n typedef struct TyphoonWindow {\n@@ -187,6 +190,14 @@ static MemTxResult cchip_read(void *opaque, hwaddr addr,\n /* PWR: Power Management Control. */\n break;\n \n+ case 0x07c0: {\n+ /* ALRM: QEMU-specific Timer Alarm Register */\n+ uint64_t cpu_index = attrs.requester_id & 3;\n+\n+ ret = s->cchip.alarm_expire[cpu_index];\n+\n+ break;\n+ }\n case 0x0c00: /* CMONCTLA */\n case 0x0c40: /* CMONCTLB */\n case 0x0c80: /* CMONCNT01 */\n@@ -352,7 +363,7 @@ static MemTxResult cchip_write(void *opaque, hwaddr addr,\n \n /* ITI can only be cleared by the write. */\n if ((newval & (1 << (i + 4))) == 0) {\n- cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER);\n+ qemu_set_irq(s->cchip.cpu_irq[i], 0);\n }\n }\n }\n@@ -439,6 +450,19 @@ static MemTxResult cchip_write(void *opaque, hwaddr addr,\n /* PWR: Power Management Control. */\n break;\n \n+ case 0x07c0: {\n+ /* ALRM: QEMU-specific Timer Alarm Register */\n+ uint64_t cpu_index = attrs.requester_id & 3;\n+ QEMUTimer *alarm_timer = s->cchip.alarm_timer[cpu_index];\n+\n+ if (val) {\n+ s->cchip.alarm_expire[cpu_index] = val;\n+ timer_mod(alarm_timer, val);\n+ } else {\n+ timer_del(alarm_timer);\n+ }\n+ break;\n+ }\n case 0x0c00: /* CMONCTLA */\n case 0x0c40: /* CMONCTLB */\n case 0x0c80: /* CMONCNT01 */\n@@ -801,7 +825,7 @@ static void typhoon_set_timer_irq(void *opaque, int irq, int level)\n /* Set the ITI bit for this cpu. */\n s->cchip.misc |= 1 << (i + 4);\n /* And signal the interrupt. */\n- cpu_interrupt(CPU(cpu), CPU_INTERRUPT_TIMER);\n+ qemu_set_irq(s->cchip.cpu_irq[i], 1);\n }\n }\n }\n@@ -814,7 +838,7 @@ static void typhoon_alarm_timer(void *opaque)\n \n /* Set the ITI bit for this cpu. */\n s->cchip.misc |= 1 << (cpu + 4);\n- cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER);\n+ qemu_set_irq(s->cchip.cpu_irq[cpu], 1);\n }\n \n static void typhoon_pcihost_instance_init(Object *obj)\n@@ -823,6 +847,8 @@ static void typhoon_pcihost_instance_init(Object *obj)\n \n s->cchip.misc = 0x800000000ull; /* Revision: Typhoon. */\n s->pchip.win[3].wba = 2; /* Window 3 SG always enabled. */\n+\n+ qdev_init_gpio_out_named(DEVICE(s), s->cchip.cpu_irq, \"cpu-irq\", 4);\n }\n \n PCIBus *typhoon_init(MemoryRegion *ram, qemu_irq *p_isa_irq,\n@@ -843,9 +869,9 @@ PCIBus *typhoon_init(MemoryRegion *ram, qemu_irq *p_isa_irq,\n AlphaCPU *cpu = cpus[i];\n s->cchip.cpu[i] = cpu;\n if (cpu != NULL) {\n- cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,\n- typhoon_alarm_timer,\n- (void *)((uintptr_t)s + i));\n+ s->cchip.alarm_timer[i] = timer_new_ns(QEMU_CLOCK_VIRTUAL,\n+ typhoon_alarm_timer,\n+ (void *)((uintptr_t)s + i));\n }\n }\n \ndiff --git a/target/alpha/cpu.c b/target/alpha/cpu.c\nindex ff053043a3..7f908a98c0 100644\n--- a/target/alpha/cpu.c\n+++ b/target/alpha/cpu.c\n@@ -27,6 +27,7 @@\n #include \"exec/target_page.h\"\n #include \"accel/tcg/cpu-ops.h\"\n #include \"fpu/softfloat.h\"\n+#include \"hw/core/cpu.h\"\n \n \n static void alpha_cpu_set_pc(CPUState *cs, vaddr value)\n@@ -203,10 +204,26 @@ static void ev67_cpu_initfn(Object *obj)\n cpu_env(CPU(obj))->amask |= AMASK_CIX | AMASK_PREFETCH;\n }\n \n+#ifndef CONFIG_USER_ONLY\n+static void alpha_cpu_irq_handler(void *opaque, int irq, int level)\n+{\n+ CPUState *cs = CPU(opaque);\n+\n+ if (level) {\n+ cpu_interrupt(cs, CPU_INTERRUPT_TIMER);\n+ } else {\n+ cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER);\n+ }\n+}\n+#endif\n+\n static void alpha_cpu_initfn(Object *obj)\n {\n CPUAlphaState *env = cpu_env(CPU(obj));\n \n+#ifndef CONFIG_USER_ONLY\n+ qdev_init_gpio_in_named(DEVICE(obj), alpha_cpu_irq_handler, \"timer-irq\", 1);\n+#endif\n /* TODO all this should be done in reset, not init */\n \n env->lock_addr = -1;\ndiff --git a/target/alpha/cpu.h b/target/alpha/cpu.h\nindex 45944e46b5..1ae1c40ce9 100644\n--- a/target/alpha/cpu.h\n+++ b/target/alpha/cpu.h\n@@ -241,9 +241,6 @@ typedef struct CPUArchState {\n uint64_t scratch[24];\n #endif\n \n- /* This alarm doesn't exist in real hardware; we wish it did. */\n- uint64_t alarm_expire;\n-\n int error_code;\n \n uint32_t features;\n@@ -261,9 +258,6 @@ struct ArchCPU {\n CPUState parent_obj;\n \n CPUAlphaState env;\n-\n- /* This alarm doesn't exist in real hardware; we wish it did. */\n- QEMUTimer *alarm_timer;\n };\n \n /**\ndiff --git a/target/alpha/helper.h b/target/alpha/helper.h\nindex 954a5c8294..c76b20eb8d 100644\n--- a/target/alpha/helper.h\n+++ b/target/alpha/helper.h\n@@ -96,5 +96,4 @@ DEF_HELPER_1(whami, i64, env)\n \n DEF_HELPER_FLAGS_0(get_vmtime, TCG_CALL_NO_RWG, i64)\n DEF_HELPER_FLAGS_0(get_walltime, TCG_CALL_NO_RWG, i64)\n-DEF_HELPER_FLAGS_2(set_alarm, TCG_CALL_NO_RWG, void, env, i64)\n #endif\ndiff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c\nindex 0e0a619975..73f26a81d1 100644\n--- a/target/alpha/sys_helper.c\n+++ b/target/alpha/sys_helper.c\n@@ -56,18 +56,6 @@ uint64_t helper_get_walltime(void)\n return qemu_clock_get_ns(rtc_clock);\n }\n \n-void helper_set_alarm(CPUAlphaState *env, uint64_t expire)\n-{\n- AlphaCPU *cpu = env_archcpu(env);\n-\n- if (expire) {\n- env->alarm_expire = expire;\n- timer_mod(cpu->alarm_timer, expire);\n- } else {\n- timer_del(cpu->alarm_timer);\n- }\n-}\n-\n uint64_t HELPER(whami)(CPUAlphaState *env)\n {\n return env_cpu(env)->cpu_index;\ndiff --git a/target/alpha/translate.c b/target/alpha/translate.c\nindex 4d22d7d5a4..cfe84f28bf 100644\n--- a/target/alpha/translate.c\n+++ b/target/alpha/translate.c\n@@ -1196,9 +1196,6 @@ static int cpu_pr_data(int pr)\n \n case 40 ... 63:\n return offsetof(CPUAlphaState, scratch[pr - 40]);\n-\n- case 251:\n- return offsetof(CPUAlphaState, alarm_expire);\n }\n return 0;\n }\n@@ -1280,14 +1277,6 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv_i64 vb, int regno)\n gen_helper_halt(vb);\n return DISAS_PC_STALE;\n \n- case 251:\n- /* ALARM */\n- if (translator_io_start(&ctx->base)) {\n- ret = DISAS_PC_STALE;\n- }\n- gen_helper_set_alarm(tcg_env, vb);\n- break;\n-\n case 7:\n /* PALBR */\n tcg_gen_st_i64(vb, tcg_env, offsetof(CPUAlphaState, palbr));\n", "prefixes": [ "RFC", "3/4" ] }