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GET /api/1.0/patches/2198333/?format=api
{ "id": 2198333, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2198333/?format=api", "project": { "id": 69, "url": "http://patchwork.ozlabs.org/api/1.0/projects/69/?format=api", "name": "QEMU powerpc development", "link_name": "qemu-ppc", "list_id": "qemu-ppc.nongnu.org", "list_email": "qemu-ppc@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260219191955.83815-7-philmd@linaro.org>", "date": "2026-02-19T19:19:08", "name": "[v2,06/50] target/riscv: Extract monitor-related code to monitor.c", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5e39db64332af3b7552cc93c1349a4356d7bd3ad", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/1.0/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-ppc/patch/20260219191955.83815-7-philmd@linaro.org/mbox/", "series": [ { "id": 492714, "url": "http://patchwork.ozlabs.org/api/1.0/series/492714/?format=api", "date": "2026-02-19T19:19:04", "name": "gdbstub: Build once on various targets (single-binary)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492714/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2198333/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=pavp8s4y;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32a;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-ppc@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-ppc.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-ppc>,\n <mailto:qemu-ppc-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-ppc>", "List-Post": "<mailto:qemu-ppc@nongnu.org>", "List-Help": "<mailto:qemu-ppc-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-ppc>,\n <mailto:qemu-ppc-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Keep riscv-qmp-cmds.c for QMP, use monitor.c for HMP.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/riscv/monitor.c | 148 +++++++++++++++++++++++++++++++++\n target/riscv/riscv-qmp-cmds.c | 150 ----------------------------------\n 2 files changed, 148 insertions(+), 150 deletions(-)", "diff": "diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c\nindex 478fd392ac6..ccb7eb44d02 100644\n--- a/target/riscv/monitor.c\n+++ b/target/riscv/monitor.c\n@@ -19,6 +19,8 @@\n */\n \n #include \"qemu/osdep.h\"\n+#include \"qemu/ctype.h\"\n+#include \"qemu/qemu-print.h\"\n #include \"cpu.h\"\n #include \"cpu_bits.h\"\n #include \"monitor/monitor.h\"\n@@ -241,3 +243,149 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)\n \n mem_info_svxx(mon, env);\n }\n+\n+/*\n+ * We have way too many potential CSRs and regs being added\n+ * regularly to register them in a static array.\n+ *\n+ * Declare an empty array instead, making get_monitor_def() use\n+ * the target_get_monitor_def() API directly.\n+ */\n+const MonitorDef monitor_defs[] = { { } };\n+const MonitorDef *target_monitor_defs(void)\n+{\n+ return monitor_defs;\n+}\n+\n+static bool reg_is_ulong_integer(CPURISCVState *env, const char *name,\n+ target_ulong *val, bool is_gprh)\n+{\n+ const char * const *reg_names;\n+ target_ulong *vals;\n+\n+ if (is_gprh) {\n+ reg_names = riscv_int_regnamesh;\n+ vals = env->gprh;\n+ } else {\n+ reg_names = riscv_int_regnames;\n+ vals = env->gpr;\n+ }\n+\n+ for (int i = 0; i < 32; i++) {\n+ g_auto(GStrv) reg_name = g_strsplit(reg_names[i], \"/\", 2);\n+\n+ g_assert(reg_name[0]);\n+ g_assert(reg_name[1]);\n+\n+ if (g_ascii_strcasecmp(reg_name[0], name) == 0 ||\n+ g_ascii_strcasecmp(reg_name[1], name) == 0) {\n+ *val = vals[i];\n+ return true;\n+ }\n+ }\n+\n+ return false;\n+}\n+\n+static bool reg_is_u64_fpu(CPURISCVState *env, const char *name, uint64_t *val)\n+{\n+ if (qemu_tolower(name[0]) != 'f') {\n+ return false;\n+ }\n+\n+ for (int i = 0; i < 32; i++) {\n+ g_auto(GStrv) reg_name = g_strsplit(riscv_fpr_regnames[i], \"/\", 2);\n+\n+ g_assert(reg_name[0]);\n+ g_assert(reg_name[1]);\n+\n+ if (g_ascii_strcasecmp(reg_name[0], name) == 0 ||\n+ g_ascii_strcasecmp(reg_name[1], name) == 0) {\n+ *val = env->fpr[i];\n+ return true;\n+ }\n+ }\n+\n+ return false;\n+}\n+\n+static bool reg_is_vreg(const char *name)\n+{\n+ if (qemu_tolower(name[0]) != 'v' || strlen(name) > 3) {\n+ return false;\n+ }\n+\n+ for (int i = 0; i < 32; i++) {\n+ if (strcasecmp(name, riscv_rvv_regnames[i]) == 0) {\n+ return true;\n+ }\n+ }\n+\n+ return false;\n+}\n+\n+int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)\n+{\n+ CPURISCVState *env = &RISCV_CPU(cs)->env;\n+ target_ulong val = 0;\n+ uint64_t val64 = 0;\n+ int i;\n+\n+ if (reg_is_ulong_integer(env, name, &val, false) ||\n+ reg_is_ulong_integer(env, name, &val, true)) {\n+ *pval = val;\n+ return 0;\n+ }\n+\n+ if (reg_is_u64_fpu(env, name, &val64)) {\n+ *pval = val64;\n+ return 0;\n+ }\n+\n+ if (reg_is_vreg(name)) {\n+ if (!riscv_cpu_cfg(env)->ext_zve32x) {\n+ return -EINVAL;\n+ }\n+\n+ qemu_printf(\"Unable to print the value of vector \"\n+ \"vreg '%s' from this API\\n\", name);\n+\n+ /*\n+ * We're returning 0 because returning -EINVAL triggers\n+ * an 'unknown register' message in exp_unary() later,\n+ * which feels ankward after our own error message.\n+ */\n+ *pval = 0;\n+ return 0;\n+ }\n+\n+ for (i = 0; i < ARRAY_SIZE(csr_ops); i++) {\n+ RISCVException res;\n+ int csrno = i;\n+\n+ /*\n+ * Early skip when possible since we're going\n+ * through a lot of NULL entries.\n+ */\n+ if (csr_ops[csrno].predicate == NULL) {\n+ continue;\n+ }\n+\n+ if (strcasecmp(csr_ops[csrno].name, name) != 0) {\n+ continue;\n+ }\n+\n+ res = riscv_csrrw_debug(env, csrno, &val, 0, 0);\n+\n+ /*\n+ * Rely on the smode, hmode, etc, predicates within csr.c\n+ * to do the filtering of the registers that are present.\n+ */\n+ if (res == RISCV_EXCP_NONE) {\n+ *pval = val;\n+ return 0;\n+ }\n+ }\n+\n+ return -EINVAL;\n+}\ndiff --git a/target/riscv/riscv-qmp-cmds.c b/target/riscv/riscv-qmp-cmds.c\nindex d5e9bec0f86..8a1856c50e0 100644\n--- a/target/riscv/riscv-qmp-cmds.c\n+++ b/target/riscv/riscv-qmp-cmds.c\n@@ -31,10 +31,6 @@\n #include \"qapi/qobject-input-visitor.h\"\n #include \"qapi/visitor.h\"\n #include \"qom/qom-qobject.h\"\n-#include \"qemu/ctype.h\"\n-#include \"qemu/qemu-print.h\"\n-#include \"monitor/hmp.h\"\n-#include \"monitor/hmp-target.h\"\n #include \"system/kvm.h\"\n #include \"system/tcg.h\"\n #include \"cpu-qom.h\"\n@@ -244,149 +240,3 @@ CpuModelExpansionInfo *qmp_query_cpu_model_expansion(CpuModelExpansionType type,\n \n return expansion_info;\n }\n-\n-/*\n- * We have way too many potential CSRs and regs being added\n- * regularly to register them in a static array.\n- *\n- * Declare an empty array instead, making get_monitor_def() use\n- * the target_get_monitor_def() API directly.\n- */\n-const MonitorDef monitor_defs[] = { { } };\n-const MonitorDef *target_monitor_defs(void)\n-{\n- return monitor_defs;\n-}\n-\n-static bool reg_is_ulong_integer(CPURISCVState *env, const char *name,\n- target_ulong *val, bool is_gprh)\n-{\n- const char * const *reg_names;\n- target_ulong *vals;\n-\n- if (is_gprh) {\n- reg_names = riscv_int_regnamesh;\n- vals = env->gprh;\n- } else {\n- reg_names = riscv_int_regnames;\n- vals = env->gpr;\n- }\n-\n- for (int i = 0; i < 32; i++) {\n- g_auto(GStrv) reg_name = g_strsplit(reg_names[i], \"/\", 2);\n-\n- g_assert(reg_name[0]);\n- g_assert(reg_name[1]);\n-\n- if (g_ascii_strcasecmp(reg_name[0], name) == 0 ||\n- g_ascii_strcasecmp(reg_name[1], name) == 0) {\n- *val = vals[i];\n- return true;\n- }\n- }\n-\n- return false;\n-}\n-\n-static bool reg_is_u64_fpu(CPURISCVState *env, const char *name, uint64_t *val)\n-{\n- if (qemu_tolower(name[0]) != 'f') {\n- return false;\n- }\n-\n- for (int i = 0; i < 32; i++) {\n- g_auto(GStrv) reg_name = g_strsplit(riscv_fpr_regnames[i], \"/\", 2);\n-\n- g_assert(reg_name[0]);\n- g_assert(reg_name[1]);\n-\n- if (g_ascii_strcasecmp(reg_name[0], name) == 0 ||\n- g_ascii_strcasecmp(reg_name[1], name) == 0) {\n- *val = env->fpr[i];\n- return true;\n- }\n- }\n-\n- return false;\n-}\n-\n-static bool reg_is_vreg(const char *name)\n-{\n- if (qemu_tolower(name[0]) != 'v' || strlen(name) > 3) {\n- return false;\n- }\n-\n- for (int i = 0; i < 32; i++) {\n- if (strcasecmp(name, riscv_rvv_regnames[i]) == 0) {\n- return true;\n- }\n- }\n-\n- return false;\n-}\n-\n-int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)\n-{\n- CPURISCVState *env = &RISCV_CPU(cs)->env;\n- target_ulong val = 0;\n- uint64_t val64 = 0;\n- int i;\n-\n- if (reg_is_ulong_integer(env, name, &val, false) ||\n- reg_is_ulong_integer(env, name, &val, true)) {\n- *pval = val;\n- return 0;\n- }\n-\n- if (reg_is_u64_fpu(env, name, &val64)) {\n- *pval = val64;\n- return 0;\n- }\n-\n- if (reg_is_vreg(name)) {\n- if (!riscv_cpu_cfg(env)->ext_zve32x) {\n- return -EINVAL;\n- }\n-\n- qemu_printf(\"Unable to print the value of vector \"\n- \"vreg '%s' from this API\\n\", name);\n-\n- /*\n- * We're returning 0 because returning -EINVAL triggers\n- * an 'unknown register' message in exp_unary() later,\n- * which feels ankward after our own error message.\n- */\n- *pval = 0;\n- return 0;\n- }\n-\n- for (i = 0; i < ARRAY_SIZE(csr_ops); i++) {\n- RISCVException res;\n- int csrno = i;\n-\n- /*\n- * Early skip when possible since we're going\n- * through a lot of NULL entries.\n- */\n- if (csr_ops[csrno].predicate == NULL) {\n- continue;\n- }\n-\n- if (strcasecmp(csr_ops[csrno].name, name) != 0) {\n- continue;\n- }\n-\n- res = riscv_csrrw_debug(env, csrno, &val, 0, 0);\n-\n- /*\n- * Rely on the smode, hmode, etc, predicates within csr.c\n- * to do the filtering of the registers that are present.\n- */\n- if (res == RISCV_EXCP_NONE) {\n- *pval = val;\n- return 0;\n- }\n- }\n-\n- return -EINVAL;\n-}\n", "prefixes": [ "v2", "06/50" ] }