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GET /api/1.0/patches/2198316/?format=api
{ "id": 2198316, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2198316/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260219191955.83815-21-philmd@linaro.org>", "date": "2026-02-19T19:19:22", "name": "[v2,20/50] target/ppc: Remove MonitorDef register entries available via gdbstub", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "bdbb68df3c284df94d95cc1fce8121cedfc371c3", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/1.0/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219191955.83815-21-philmd@linaro.org/mbox/", "series": [ { "id": 492715, "url": "http://patchwork.ozlabs.org/api/1.0/series/492715/?format=api", "date": "2026-02-19T19:19:03", "name": "gdbstub: Build once on various targets (single-binary)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492715/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2198316/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=GqIoTdrK;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::336;\n envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "All these registers are already provided by via gdbstub parsed XML\nand handler by the gdb_get_register() helper in the monitor/hmp.c\nfile. Remove as now unreachable code.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/ppc/ppc-qmp-cmds.c | 132 --------------------------------------\n 1 file changed, 132 deletions(-)", "diff": "diff --git a/target/ppc/ppc-qmp-cmds.c b/target/ppc/ppc-qmp-cmds.c\nindex 7022564604f..66c3bcb2c38 100644\n--- a/target/ppc/ppc-qmp-cmds.c\n+++ b/target/ppc/ppc-qmp-cmds.c\n@@ -33,54 +33,6 @@\n #include \"cpu-models.h\"\n #include \"cpu-qom.h\"\n \n-static target_long monitor_get_ccr(Monitor *mon, const struct MonitorDef *md,\n- int val)\n-{\n- CPUArchState *env = mon_get_cpu_env(mon);\n- unsigned int u;\n-\n- u = ppc_get_cr(env);\n-\n- return u;\n-}\n-\n-static target_long monitor_get_xer(Monitor *mon, const struct MonitorDef *md,\n- int val)\n-{\n- CPUArchState *env = mon_get_cpu_env(mon);\n- return cpu_read_xer(env);\n-}\n-\n-static target_long monitor_get_decr(Monitor *mon, const struct MonitorDef *md,\n- int val)\n-{\n- CPUArchState *env = mon_get_cpu_env(mon);\n- if (!env->tb_env) {\n- return 0;\n- }\n- return cpu_ppc_load_decr(env);\n-}\n-\n-static target_long monitor_get_tbu(Monitor *mon, const struct MonitorDef *md,\n- int val)\n-{\n- CPUArchState *env = mon_get_cpu_env(mon);\n- if (!env->tb_env) {\n- return 0;\n- }\n- return cpu_ppc_load_tbu(env);\n-}\n-\n-static target_long monitor_get_tbl(Monitor *mon, const struct MonitorDef *md,\n- int val)\n-{\n- CPUArchState *env = mon_get_cpu_env(mon);\n- if (!env->tb_env) {\n- return 0;\n- }\n- return cpu_ppc_load_tbl(env);\n-}\n-\n void hmp_info_tlb(Monitor *mon, const QDict *qdict)\n {\n CPUArchState *env1 = mon_get_cpu_env(mon);\n@@ -92,90 +44,6 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)\n dump_mmu(env1);\n }\n \n-const MonitorDef monitor_defs[] = {\n- { \"fpscr\", offsetof(CPUPPCState, fpscr) },\n- /* Next instruction pointer */\n- { \"nip|pc\", offsetof(CPUPPCState, nip) },\n- { \"lr\", offsetof(CPUPPCState, lr) },\n- { \"ctr\", offsetof(CPUPPCState, ctr) },\n- { \"decr\", 0, &monitor_get_decr, },\n- { \"ccr|cr\", 0, &monitor_get_ccr, },\n- /* Machine state register */\n- { \"xer\", 0, &monitor_get_xer },\n- { \"msr\", offsetof(CPUPPCState, msr) },\n- { \"tbu\", 0, &monitor_get_tbu, },\n-#if defined(TARGET_PPC64)\n- { \"tb\", 0, &monitor_get_tbl, },\n-#else\n- { \"tbl\", 0, &monitor_get_tbl, },\n-#endif\n- { NULL },\n-};\n-\n-const MonitorDef *target_monitor_defs(void)\n-{\n- return monitor_defs;\n-}\n-\n-static int ppc_cpu_get_reg_num(const char *numstr, int maxnum, int *pregnum)\n-{\n- int regnum;\n- char *endptr = NULL;\n-\n- if (!*numstr) {\n- return false;\n- }\n-\n- regnum = strtoul(numstr, &endptr, 10);\n- if (*endptr || (regnum >= maxnum)) {\n- return false;\n- }\n- *pregnum = regnum;\n-\n- return true;\n-}\n-\n-int target_get_monitor_def(CPUState *cs, const char *name, uint64_t *pval)\n-{\n- int i, regnum;\n- CPUPPCState *env = cpu_env(cs);\n-\n- /* General purpose registers */\n- if ((qemu_tolower(name[0]) == 'r') &&\n- ppc_cpu_get_reg_num(name + 1, ARRAY_SIZE(env->gpr), ®num)) {\n- *pval = env->gpr[regnum];\n- return 0;\n- }\n-\n- /* Floating point registers */\n- if ((qemu_tolower(name[0]) == 'f') &&\n- ppc_cpu_get_reg_num(name + 1, 32, ®num)) {\n- *pval = *cpu_fpr_ptr(env, regnum);\n- return 0;\n- }\n-\n- /* Special purpose registers */\n- for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) {\n- ppc_spr_t *spr = &env->spr_cb[i];\n-\n- if (spr->name && (strcasecmp(name, spr->name) == 0)) {\n- *pval = env->spr[i];\n- return 0;\n- }\n- }\n-\n- /* Segment registers */\n-#if !defined(CONFIG_USER_ONLY)\n- if ((strncasecmp(name, \"sr\", 2) == 0) &&\n- ppc_cpu_get_reg_num(name + 2, ARRAY_SIZE(env->sr), ®num)) {\n- *pval = env->sr[regnum];\n- return 0;\n- }\n-#endif\n-\n- return -EINVAL;\n-}\n-\n CpuModelExpansionInfo *\n qmp_query_cpu_model_expansion(CpuModelExpansionType type,\n CpuModelInfo *model,\n", "prefixes": [ "v2", "20/50" ] }