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GET /api/1.0/patches/2198278/?format=api
{ "id": 2198278, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2198278/?format=api", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.0/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260219175130.2839234-9-dario.binacchi@amarulasolutions.com>", "date": "2026-02-19T17:51:19", "name": "[8/8] video: support Rocktech RK050HR345-CT106A panel", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "2b8578c72110f30ba79f9a92fa20c2962571d100", "submitter": { "id": 83038, "url": "http://patchwork.ozlabs.org/api/1.0/people/83038/?format=api", "name": "Dario Binacchi", "email": "dario.binacchi@amarulasolutions.com" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/1.0/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260219175130.2839234-9-dario.binacchi@amarulasolutions.com/mbox/", "series": [ { "id": 492708, "url": "http://patchwork.ozlabs.org/api/1.0/series/492708/?format=api", "date": "2026-02-19T17:51:11", "name": "video: support Rocktech RK050HR345-CT106A panel", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/492708/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2198278/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com\n header.a=rsa-sha256 header.s=google header.b=Eu8EcdPB;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=amarulasolutions.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com\n header.b=\"Eu8EcdPB\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=none dis=none)\n header.from=amarulasolutions.com", "phobos.denx.de; spf=pass\n smtp.mailfrom=dario.binacchi@amarulasolutions.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fH1F94WJfz1xpl\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 20 Feb 2026 04:53:01 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 7341A83E69;\n\tThu, 19 Feb 2026 18:52:30 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 20F0383D8A; Thu, 19 Feb 2026 18:52:29 +0100 (CET)", "from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com\n [IPv6:2a00:1450:4864:20::32f])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 058EC83E69\n for <u-boot@lists.denx.de>; Thu, 19 Feb 2026 18:52:26 +0100 (CET)", "by mail-wm1-x32f.google.com with SMTP id\n 5b1f17b1804b1-483770e0b25so13129065e9.0\n for <u-boot@lists.denx.de>; Thu, 19 Feb 2026 09:52:26 -0800 (PST)", "from dario-ThinkPad-P14s-Gen-5.homenet.telecomitalia.it\n (host-95-248-31-95.retail.telecomitalia.it. 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This model\nuses an Ilitek ILI9806E controller over the SPI bus for initialization\nand register configuration only.\n\nThe driver is designed to be easily extensible to support other panels\nwith different sequences and timings by providing a specific descriptor\nstructure for each model.\n\nSigned-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>\n---\n\n drivers/video/Kconfig | 8 +\n drivers/video/Makefile | 1 +\n drivers/video/ilitek-ili9806e.c | 354 ++++++++++++++++++++++++++++++++\n 3 files changed, 363 insertions(+)\n create mode 100644 drivers/video/ilitek-ili9806e.c", "diff": "diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig\nindex 08c9b0207884..c78d6540855a 100644\n--- a/drivers/video/Kconfig\n+++ b/drivers/video/Kconfig\n@@ -552,6 +552,14 @@ config VIDEO_LCD_HIMAX_HX8394\n \tSay Y here if you want to enable support for Himax HX8394\n \tdsi 4dl panel.\n \n+config VIDEO_LCD_ILITEK_ILI9806E\n+\ttristate \"Ilitek ILI9806E-based panels\"\n+\tdepends on PANEL && BACKLIGHT\n+\thelp\n+\t Say Y here if you want to enable support for panels base on\n+\t the Ilitek ILI9806E controller. Currently only the DBI panel\n+\t is implemented.\n+\n config VIDEO_LCD_MOT\n \ttristate \"Atrix 4G and Droid X2 540x960 DSI video mode panel\"\n \tdepends on PANEL && BACKLIGHT\ndiff --git a/drivers/video/Makefile b/drivers/video/Makefile\nindex 984768ea156d..74846a8106e4 100644\n--- a/drivers/video/Makefile\n+++ b/drivers/video/Makefile\n@@ -61,6 +61,7 @@ obj-$(CONFIG_VIDEO_LCD_ENDEAVORU) += endeavoru-panel.o\n obj-$(CONFIG_VIDEO_LCD_HIMAX_HX8394) += himax-hx8394.o\n obj-$(CONFIG_VIDEO_LCD_HITACHI_TX10D07VM0BAA) += hitachi-tx10d07vm0baa.o\n obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o\n+obj-$(CONFIG_VIDEO_LCD_ILITEK_ILI9806E) += ilitek-ili9806e.o\n obj-$(CONFIG_VIDEO_LCD_LG_LD070WX3) += lg-ld070wx3.o\n obj-$(CONFIG_VIDEO_LCD_LG_LH400WV3) += lg-lh400wv3-sd04.o\n obj-$(CONFIG_VIDEO_LCD_MOT) += mot-panel.o\ndiff --git a/drivers/video/ilitek-ili9806e.c b/drivers/video/ilitek-ili9806e.c\nnew file mode 100644\nindex 000000000000..e1b27e12dde5\n--- /dev/null\n+++ b/drivers/video/ilitek-ili9806e.c\n@@ -0,0 +1,354 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2026 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>\n+ */\n+\n+#include <backlight.h>\n+#include <dm.h>\n+#include <mipi_display.h>\n+#include <panel.h>\n+#include <spi.h>\n+#include <asm/gpio.h>\n+#include <dm/device_compat.h>\n+#include <linux/delay.h>\n+#include <power/regulator.h>\n+\n+struct ilitek_ili9806e_priv {\n+\tstruct udevice *vdd;\n+\tstruct udevice *backlight;\n+\tstruct gpio_desc reset_gpio;\n+\tconst struct ilitek_ili9806e_desc *desc;\n+};\n+\n+struct ilitek_ili9806e_desc {\n+\tconst struct display_timing timing;\n+\tvoid (*init_sequence)(struct udevice *dev);\n+};\n+\n+static int ilitek_ili9806e_dcs_write(struct udevice *dev, u8 cmd, const u8 *seq, int len)\n+{\n+\tu16 data[16];\n+\tint i, ret;\n+\n+\tif ((len + 1) > ARRAY_SIZE(data)) {\n+\t\tdev_err(dev, \"Command length (%d) exceeds buffer size (%lu)\\n\",\n+\t\t\tlen + 1, ARRAY_SIZE(data));\n+\t\treturn -EMSGSIZE;\n+\t}\n+\n+\tdata[0] = cmd;\n+\tif (len) {\n+\t\tfor (i = 0; i < len; i++)\n+\t\t\tdata[i + 1] = seq[i] | 0x0100;\n+\t}\n+\n+\tret = dm_spi_xfer(dev, (len + 1) * 8 * sizeof(u16), data, NULL,\n+\t\t\t SPI_XFER_ONCE);\n+\treturn 0;\n+}\n+\n+#define ilitek_ili9806e_dcs_write_seq(dev, cmd, seq...)\t\t\\\n+({\t\t\t\t\t\t\t\t\\\n+\tstatic const u8 b[] = { seq };\t\t\t\t\\\n+\tilitek_ili9806e_dcs_write(dev, cmd, b, ARRAY_SIZE(b));\t\\\n+})\n+\n+static int ilitek_ili9806e_enable_backlight(struct udevice *dev)\n+{\n+\tstruct ilitek_ili9806e_priv *priv = dev_get_priv(dev);\n+\tconst struct ilitek_ili9806e_desc *desc = priv->desc;\n+\n+\tdesc->init_sequence(dev);\n+\n+\treturn panel_set_backlight(dev, BACKLIGHT_DEFAULT);\n+}\n+\n+static int ilitek_ili9806e_set_backlight(struct udevice *dev, int percent)\n+{\n+\tstruct ilitek_ili9806e_priv *priv = dev_get_priv(dev);\n+\tint ret;\n+\n+\tret = backlight_enable(priv->backlight);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Cannot enable backlight\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = backlight_set_brightness(priv->backlight, percent);\n+\tif (ret)\n+\t\tdev_err(dev, \"Cannot set backlight brightness\\n\");\n+\n+\treturn ret;\n+}\n+\n+static int ilitek_ili9806e_get_display_timing(struct udevice *dev,\n+\t\t\t\t\t struct display_timing *timing)\n+{\n+\tstruct ilitek_ili9806e_priv *priv = dev_get_priv(dev);\n+\n+\tmemcpy(timing, &priv->desc->timing, sizeof(*timing));\n+\treturn 0;\n+}\n+\n+static int ilitek_ili9806e_of_to_plat(struct udevice *dev)\n+{\n+\tstruct ilitek_ili9806e_priv *priv = dev_get_priv(dev);\n+\tint ret;\n+\n+\tif (CONFIG_IS_ENABLED(DM_REGULATOR)) {\n+\t\tret = device_get_supply_regulator(dev, \"vdd-supply\", &priv->vdd);\n+\t\tif (ret) {\n+\t\t\tdev_err(dev, \"Cannot get vdd supply\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\tret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,\n+\t\t\t\t\t \"backlight\", &priv->backlight);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Cannot get backlight\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = gpio_request_by_name(dev, \"reset-gpios\", 0,\n+\t\t\t\t &priv->reset_gpio, GPIOD_IS_OUT);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Cannot get reset GPIO\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int ilitek_ili9806e_hw_init(struct udevice *dev)\n+{\n+\tstruct ilitek_ili9806e_priv *priv = dev_get_priv(dev);\n+\tint ret;\n+\n+\tret = dm_gpio_set_value(&priv->reset_gpio, 1);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Cannot enter reset\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = regulator_set_enable_if_allowed(priv->vdd, 1);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Cannot enable vdd-supply\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tmdelay(20);\n+\n+\tret = dm_gpio_set_value(&priv->reset_gpio, 0);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Cannot exit reset\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tmdelay(20);\n+\n+\treturn 0;\n+}\n+\n+static int ilitek_ili9806e_probe(struct udevice *dev)\n+{\n+\tstruct ilitek_ili9806e_priv *priv = dev_get_priv(dev);\n+\tstruct spi_slave *slave = dev_get_parent_priv(dev);\n+\tint ret;\n+\n+\tret = spi_set_wordlen(slave, 9);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Cannot set SPI.bits_per_word\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tret = spi_claim_bus(slave);\n+\tif (ret) {\n+\t\tdev_err(dev, \"Cannot get SPI bus\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tpriv->desc = (struct ilitek_ili9806e_desc *)dev_get_driver_data(dev);\n+\treturn ilitek_ili9806e_hw_init(dev);\n+}\n+\n+static const struct panel_ops ilitek_ili9806e_ops = {\n+\t.enable_backlight = ilitek_ili9806e_enable_backlight,\n+\t.set_backlight = ilitek_ili9806e_set_backlight,\n+\t.get_display_timing = ilitek_ili9806e_get_display_timing,\n+};\n+\n+static void rk050hr345_ct106a_init(struct udevice *dev)\n+{\n+\t/* Switch to page 1 */\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01);\n+\t/* Interface Settings */\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x08, 0x10);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x21, 0x01);\n+\t/* Panel Settings */\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x30, 0x01);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x31, 0x00);\n+\t/* Power Control */\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x40, 0x15);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x41, 0x44);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x42, 0x03);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x43, 0x09);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x44, 0x09);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x50, 0x78);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x51, 0x78);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x52, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x53, 0x3a);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x57, 0x50);\n+\t/* Timing Control */\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x60, 0x07);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x61, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x62, 0x08);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x63, 0x00);\n+\t/* Gamma Settings */\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xa0, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xa1, 0x03);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xa2, 0x0b);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xa3, 0x0f);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xa4, 0x0b);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xa5, 0x1b);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xa6, 0x0a);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xa7, 0x0a);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xa8, 0x02);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xa9, 0x07);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xaa, 0x05);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xab, 0x03);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xac, 0x0e);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xad, 0x32);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xae, 0x2d);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xaf, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xc0, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xc1, 0x03);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xc2, 0x0e);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xc3, 0x10);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xc4, 0x09);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xc5, 0x17);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xc6, 0x09);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xc7, 0x07);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xc8, 0x04);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xc9, 0x09);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xca, 0x06);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xcb, 0x06);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xcc, 0x0c);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xcd, 0x25);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xce, 0x20);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xcf, 0x00);\n+\n+\t/* Switch to page 6 */\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xff, 0xff, 0x98, 0x06, 0x04, 0x06);\n+\t/* GIP settings */\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x00, 0x21);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x01, 0x09);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x02, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x03, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x04, 0x01);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x05, 0x01);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x06, 0x80);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x07, 0x05);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x08, 0x02);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x09, 0x80);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x0a, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x0b, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x0c, 0x0a);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x0d, 0x0a);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x0e, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x0f, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x10, 0xe0);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x11, 0xe4);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x12, 0x04);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x13, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x14, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x15, 0xc0);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x16, 0x08);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x17, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x18, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x19, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x1a, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x1b, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x1c, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x1d, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x20, 0x01);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x21, 0x23);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x22, 0x45);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x23, 0x67);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x24, 0x01);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x25, 0x23);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x26, 0x45);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x27, 0x67);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x30, 0x01);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x31, 0x11);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x32, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x33, 0xee);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x34, 0xff);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x35, 0xbb);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x36, 0xca);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x37, 0xdd);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x38, 0xac);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x39, 0x76);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x3a, 0x67);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x3b, 0x22);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x3c, 0x22);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x3d, 0x22);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x3e, 0x22);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x3f, 0x22);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x40, 0x22);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x52, 0x10);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x53, 0x10);\n+\n+\t/* Switch to page 7 */\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x17, 0x22);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0x02, 0x77);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xe1, 0x79);\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xb3, 0x10);\n+\n+\t/* Switch to page 0 */\n+\tilitek_ili9806e_dcs_write_seq(dev, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, MIPI_DCS_SET_ADDRESS_MODE, 0x00);\n+\tilitek_ili9806e_dcs_write_seq(dev, MIPI_DCS_EXIT_SLEEP_MODE);\n+\n+\tmdelay(120);\n+\n+\tilitek_ili9806e_dcs_write_seq(dev, MIPI_DCS_SET_DISPLAY_ON);\n+\n+\tmdelay(120);\n+}\n+\n+static const struct ilitek_ili9806e_desc rk050hr345_ct106a_desc = {\n+\t.timing = {\n+\t\t.pixelclock.typ = 27000000,\n+\t\t.hactive.typ = 480,\n+\t\t.hfront_porch.typ = 10,\n+\t\t.hback_porch.typ = 10,\n+\t\t.hsync_len.typ = 10,\n+\t\t.vactive.typ = 854,\n+\t\t.vfront_porch.typ = 10,\n+\t\t.vback_porch.typ = 10,\n+\t\t.vsync_len.typ = 10,\n+\t\t.flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,\n+\t},\n+\t.init_sequence = rk050hr345_ct106a_init,\n+};\n+\n+static const struct udevice_id ilitek_ili9806e_ids[] = {\n+\t{\n+\t\t.compatible = \"rocktech,rk050hr345-ct106a\",\n+\t\t.data = (ulong)&rk050hr345_ct106a_desc,\n+\t},\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(ilitek_ili9806e) = {\n+\t.name\t\t= \"ilitek_ili9806e\",\n+\t.id\t\t= UCLASS_PANEL,\n+\t.of_match\t= ilitek_ili9806e_ids,\n+\t.ops\t\t= &ilitek_ili9806e_ops,\n+\t.of_to_plat\t= ilitek_ili9806e_of_to_plat,\n+\t.probe\t\t= ilitek_ili9806e_probe,\n+\t.priv_auto\t= sizeof(struct ilitek_ili9806e_priv),\n+\t.flags\t\t= DM_FLAG_PRE_RELOC,\n+};\n", "prefixes": [ "8/8" ] }