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GET /api/1.0/patches/2198261/?format=api
{ "id": 2198261, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2198261/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260219171810.602667-8-alex.bennee@linaro.org>", "date": "2026-02-19T17:18:03", "name": "[RFC,v2,07/14] hw/mips: defer finalising gcr_base until reset time", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d9eb136ee56815b8b3681f6cb770750bd268feae", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/1.0/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219171810.602667-8-alex.bennee@linaro.org/mbox/", "series": [ { "id": 492705, "url": "http://patchwork.ozlabs.org/api/1.0/series/492705/?format=api", "date": "2026-02-19T17:17:57", "name": "cpu_reset clean-ups for arm, alpha, mips, m68k and tricore", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492705/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2198261/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=EYz2lv8n;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::631;\n envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x631.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Currently the cpu_reset() in mips_cpu_realizefn() hides an implicit\nsequencing requirement when setting gcr_base. Without it we barf\nbecause we end up setting the region between 0x0-0x000000001fbfffff\nwhich trips over a qtest that accesses the GCR during \"memsave 0 4096\n/dev/null\".\n\nBy moving to the reset phase we have to drop the property lest we are\nadmonished for \"Attempting to set...after it was realized\" but there\ndoesn't seem to be a need to expose the property anyway.\n\nNB: it would be safer if I could guarantee the place in the reset tree\nbut I haven't quite grokked how to do that yet. Currently I see this\nsequence when testing:\n\n env MALLOC_PERTURB_=43 G_TEST_DBUS_DAEMON=/home/alex/lsrc/qemu.git/tests/dbus-vmstate-daemon.sh UBSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print_stacktrace=1 QTEST_QEMU_IMG=./qemu-img QTEST_QEMU_BINARY=./qemu-system-mips64el SPEED=thorough MESON_TEST_ITERATION=1 MSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print_stacktrace=1 PYTHON=/home/alex/lsrc/qemu.git/builds/all/pyvenv/bin/python3 QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon ASAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1 G_TEST_SLOW=1 RUST_BACKTRACE=1 /home/alex/lsrc/qemu.git/builds/all/tests/qtest/test-hmp --tap -p /mips64el/hmp/boston\n TAP version 14\n # random seed: R02S0d3b1a4f1aef5198107851bdee539e7d\n # Start of mips64el tests\n # Start of hmp tests\n # starting QEMU: exec ./qemu-system-mips64el -qtest unix:/tmp/qtest-530181.sock -qtest-log /dev/null -chardev socket,path=/tmp/qtest-530181.qmp,id=char0 -mon chardev=char0,mode=control -display none -audio none -run-with exit-with-parent=on -S -M boston -accel qtest\n main_cpu_reset: dbg\n mips_gcr_reset: dbg\n mps_reset_exit: dbg\n ok 1 /mips64el/hmp/boston\n # End of hmp tests\n # End of mips64el tests\n 1..1\n\nCc: Peter Maydell <peter.maydell@linaro.org>\nMessage-ID: <20260108143423.1378674-9-alex.bennee@linaro.org>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n\n---\nv2\n - use proper 3-phase reset\n---\n include/hw/mips/cps.h | 14 +++++++++++++-\n hw/mips/cps.c | 26 +++++++++++++++++---------\n hw/misc/mips_cmgcr.c | 1 -\n 3 files changed, 30 insertions(+), 11 deletions(-)", "diff": "diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h\nindex 878b4d819f4..1084a10de0f 100644\n--- a/include/hw/mips/cps.h\n+++ b/include/hw/mips/cps.h\n@@ -30,7 +30,7 @@\n #include \"qom/object.h\"\n \n #define TYPE_MIPS_CPS \"mips-cps\"\n-OBJECT_DECLARE_SIMPLE_TYPE(MIPSCPSState, MIPS_CPS)\n+OBJECT_DECLARE_TYPE(MIPSCPSState, MIPSCPSClass, MIPS_CPS)\n \n struct MIPSCPSState {\n SysBusDevice parent_obj;\n@@ -48,6 +48,18 @@ struct MIPSCPSState {\n Clock *clock;\n };\n \n+/*\n+ * MIPSCPSClass:\n+ * @parent_phases: The parent class' reset phase handlers.\n+ *\n+ * A Coherent Processing System model.\n+ */\n+struct MIPSCPSClass {\n+ SysBusDeviceClass parent_class;\n+\n+ ResettablePhases parent_phases;\n+};\n+\n qemu_irq get_cps_irq(MIPSCPSState *cps, int pin_number);\n \n #endif\ndiff --git a/hw/mips/cps.c b/hw/mips/cps.c\nindex 620ee972f8f..23918147276 100644\n--- a/hw/mips/cps.c\n+++ b/hw/mips/cps.c\n@@ -55,6 +55,17 @@ static void main_cpu_reset(void *opaque)\n cpu_reset(cs);\n }\n \n+static void mps_reset_exit(Object *obj, ResetType type)\n+{\n+ MIPSCPSState *s = MIPS_CPS(obj);\n+ hwaddr gcr_base;\n+\n+ /* Global Configuration Registers - only valid once the CPU has been reset */\n+ gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4;\n+ memory_region_add_subregion(&s->container, gcr_base,\n+ sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));\n+}\n+\n static bool cpu_mips_itu_supported(CPUMIPSState *env)\n {\n bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || ase_mt_available(env);\n@@ -65,7 +76,6 @@ static bool cpu_mips_itu_supported(CPUMIPSState *env)\n static void mips_cps_realize(DeviceState *dev, Error **errp)\n {\n MIPSCPSState *s = MIPS_CPS(dev);\n- target_ulong gcr_base;\n bool itu_present = false;\n \n if (!clock_get(s->clock)) {\n@@ -144,16 +154,11 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)\n memory_region_add_subregion(&s->container, 0,\n sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));\n \n- /* Global Configuration Registers */\n- gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4;\n-\n object_initialize_child(OBJECT(dev), \"gcr\", &s->gcr, TYPE_MIPS_GCR);\n object_property_set_uint(OBJECT(&s->gcr), \"num-vp\", s->num_vp,\n &error_abort);\n object_property_set_int(OBJECT(&s->gcr), \"gcr-rev\", 0x800,\n &error_abort);\n- object_property_set_int(OBJECT(&s->gcr), \"gcr-base\", gcr_base,\n- &error_abort);\n object_property_set_link(OBJECT(&s->gcr), \"gic\", OBJECT(&s->gic.mr),\n &error_abort);\n object_property_set_link(OBJECT(&s->gcr), \"cpc\", OBJECT(&s->cpc.mr),\n@@ -161,9 +166,6 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)\n if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {\n return;\n }\n-\n- memory_region_add_subregion(&s->container, gcr_base,\n- sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));\n }\n \n static const Property mips_cps_properties[] = {\n@@ -176,8 +178,13 @@ static const Property mips_cps_properties[] = {\n static void mips_cps_class_init(ObjectClass *klass, const void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(klass);\n+ MIPSCPSClass *mcs = MIPS_CPS_CLASS(klass);\n+ ResettableClass *rc = RESETTABLE_CLASS(klass);\n \n dc->realize = mips_cps_realize;\n+\n+ resettable_class_set_parent_phases(rc, NULL, NULL, mps_reset_exit,\n+ &mcs->parent_phases);\n device_class_set_props(dc, mips_cps_properties);\n }\n \n@@ -187,6 +194,7 @@ static const TypeInfo mips_cps_info = {\n .instance_size = sizeof(MIPSCPSState),\n .instance_init = mips_cps_init,\n .class_init = mips_cps_class_init,\n+ .class_size = sizeof(MIPSCPSClass),\n };\n \n static void mips_cps_register_types(void)\ndiff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c\nindex 3e262e828bc..9e1c8d26ea5 100644\n--- a/hw/misc/mips_cmgcr.c\n+++ b/hw/misc/mips_cmgcr.c\n@@ -214,7 +214,6 @@ static const VMStateDescription vmstate_mips_gcr = {\n static const Property mips_gcr_properties[] = {\n DEFINE_PROP_UINT32(\"num-vp\", MIPSGCRState, num_vps, 1),\n DEFINE_PROP_INT32(\"gcr-rev\", MIPSGCRState, gcr_rev, 0x800),\n- DEFINE_PROP_UINT64(\"gcr-base\", MIPSGCRState, gcr_base, GCR_BASE_ADDR),\n DEFINE_PROP_LINK(\"gic\", MIPSGCRState, gic_mr, TYPE_MEMORY_REGION,\n MemoryRegion *),\n DEFINE_PROP_LINK(\"cpc\", MIPSGCRState, cpc_mr, TYPE_MEMORY_REGION,\n", "prefixes": [ "RFC", "v2", "07/14" ] }