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GET /api/1.0/patches/2198254/?format=api
{ "id": 2198254, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2198254/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260219171810.602667-3-alex.bennee@linaro.org>", "date": "2026-02-19T17:17:58", "name": "[RFC,v2,02/14] target/m68k: initialise pc/sp vector during reset", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d4050b593fad6a3c2b3c53d46f4102b61b2148c3", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/1.0/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219171810.602667-3-alex.bennee@linaro.org/mbox/", "series": [ { "id": 492705, "url": "http://patchwork.ozlabs.org/api/1.0/series/492705/?format=api", "date": "2026-02-19T17:17:57", "name": "cpu_reset clean-ups for arm, alpha, mips, m68k and tricore", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492705/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2198254/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=n35egehw;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::529;\n envelope-from=alex.bennee@linaro.org; helo=mail-ed1-x529.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "All 68k chips should be able to follow the architectural behaviour on\nreset which is to load the initial sp/pc from the first 8 bytes of the\naddress space.\n\nTo avoid any potential issues with un-reset memory controllers we\npunt the final setting of the register to the exit phase when\neverything else is guaranteed to have been through the hold phase.\n\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n---\n target/m68k/cpu.c | 25 +++++++++++++++++++++----\n 1 file changed, 21 insertions(+), 4 deletions(-)", "diff": "diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c\nindex d849a4a90fc..0dce8ef282e 100644\n--- a/target/m68k/cpu.c\n+++ b/target/m68k/cpu.c\n@@ -25,6 +25,7 @@\n \n #ifndef CONFIG_USER_ONLY\n #include \"migration/vmstate.h\"\n+#include \"system/memory.h\"\n #endif\n \n #include \"cpu.h\"\n@@ -174,9 +175,25 @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)\n }\n cpu_m68k_set_fpcr(env, 0);\n env->fpsr = 0;\n+}\n \n- /* TODO: We should set PC from the interrupt vector. */\n- env->pc = 0;\n+/*\n+ * We defer the final setting of the PC to the exit phase to ensure\n+ * if any memory controllers need to be reset they are before we read\n+ * the initial reset vector. This is a NOP for user-mode which will\n+ * set the PC in init_main_thread() after the CPU is reset.\n+ */\n+static void m68k_cpu_reset_exit(Object *obj, ResetType type)\n+{\n+#ifndef CONFIG_USER_ONLY\n+ CPUState *cs = CPU(obj);\n+ CPUM68KState *env = cpu_env(cs);\n+\n+ env->aregs[7] = address_space_ldl_be(cs->as, 0,\n+ MEMTXATTRS_UNSPECIFIED, NULL);\n+ env->pc = address_space_ldl_be(cs->as, 4,\n+ MEMTXATTRS_UNSPECIFIED, NULL);\n+#endif\n }\n \n static void m68k_cpu_disas_set_info(const CPUState *cs, disassemble_info *info)\n@@ -396,7 +413,6 @@ static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)\n \n m68k_cpu_init_gdb(cpu);\n \n- cpu_reset(cs);\n qemu_init_vcpu(cs);\n \n mcc->parent_realize(dev, errp);\n@@ -641,7 +657,8 @@ static void m68k_cpu_class_init(ObjectClass *c, const void *data)\n \n device_class_set_parent_realize(dc, m68k_cpu_realizefn,\n &mcc->parent_realize);\n- resettable_class_set_parent_phases(rc, NULL, m68k_cpu_reset_hold, NULL,\n+ resettable_class_set_parent_phases(rc, NULL,\n+ m68k_cpu_reset_hold, m68k_cpu_reset_exit,\n &mcc->parent_phases);\n \n cc->class_by_name = m68k_cpu_class_by_name;\n", "prefixes": [ "RFC", "v2", "02/14" ] }