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GET /api/1.0/patches/2198224/?format=api
{ "id": 2198224, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2198224/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260219144901.3317747-5-ruslichenko.r@gmail.com>", "date": "2026-02-19T14:48:51", "name": "[v2,23/33] target/arm/cpu: add fdt support for armv8-timer", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "dd176729824c1013d3f62ca30925a9bd01e3c9cb", "submitter": { "id": 92275, "url": "http://patchwork.ozlabs.org/api/1.0/people/92275/?format=api", "name": "Ruslan Ruslichenko", "email": "ruslichenko.r@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219144901.3317747-5-ruslichenko.r@gmail.com/mbox/", "series": [ { "id": 492690, "url": "http://patchwork.ozlabs.org/api/1.0/series/492690/?format=api", "date": "2026-02-19T14:33:04", "name": "hw/arm: Introduce generic FDT-driven machine", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492690/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2198224/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=WYi/cIpV;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fGxFw4Ddkz1xpl\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 20 Feb 2026 01:53:24 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1vt5MN-00044G-3X; Thu, 19 Feb 2026 09:50:31 -0500", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <ruslichenko.r@gmail.com>)\n id 1vt5Lv-0003lX-1r\n for qemu-devel@nongnu.org; Thu, 19 Feb 2026 09:50:12 -0500", "from mail-wr1-x436.google.com ([2a00:1450:4864:20::436])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <ruslichenko.r@gmail.com>)\n id 1vt5Lp-00083w-Ep\n for qemu-devel@nongnu.org; Thu, 19 Feb 2026 09:50:00 -0500", "by mail-wr1-x436.google.com with SMTP id\n ffacd0b85a97d-436e87589e8so1064999f8f.3\n for <qemu-devel@nongnu.org>; Thu, 19 Feb 2026 06:49:47 -0800 (PST)", "from thinkpad-t470s.. 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Iglesias\" <edgar.iglesias@gmail.com>,\n Ruslan_Ruslichenko@epam.com, balaton@eik.bme.hu", "Subject": "[PATCH v2 23/33] target/arm/cpu: add fdt support for armv8-timer", "Date": "Thu, 19 Feb 2026 15:48:51 +0100", "Message-ID": "<20260219144901.3317747-5-ruslichenko.r@gmail.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260219144901.3317747-1-ruslichenko.r@gmail.com>", "References": "<20260219143332.3316679-1-ruslichenko.r@gmail.com>\n <20260219144901.3317747-1-ruslichenko.r@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::436;\n envelope-from=ruslichenko.r@gmail.com; helo=mail-wr1-x436.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Ruslan Ruslichenko <Ruslan_Ruslichenko@epam.com>\n\nImplement FDT compatibility, so that timer can initilize\nand wire irqs based on device tree information.\n\nSigned-off-by: Ruslan Ruslichenko <Ruslan_Ruslichenko@epam.com>\n---\n target/arm/cpu.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 115 insertions(+)", "diff": "diff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 7542444b18..6e68aa457e 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -54,6 +54,8 @@\n #include \"target/arm/gtimer.h\"\n \n #include \"trace.h\"\n+#include \"hw/core/fdt_generic_util.h\"\n+\n \n static void arm_cpu_set_pc(CPUState *cs, vaddr value)\n {\n@@ -2455,3 +2457,116 @@ static void arm_cpu_register_types(void)\n }\n \n type_init(arm_cpu_register_types)\n+\n+#ifndef CONFIG_USER_ONLY\n+\n+static Object *fdt_armv8_timer_get_intc(FDTMachineInfo *fdti, char *node_path)\n+{\n+ char intc_node_path[DT_PATH_LENGTH];\n+ uint32_t intc_phandle;\n+ Error *errp = NULL;\n+ DeviceState *intc;\n+\n+ intc_phandle = qemu_fdt_getprop_cell_inherited(fdti->fdt, node_path,\n+ \"interrupt-parent\",\n+ 0, &errp);\n+\n+ /* There must be an interrupt-parent */\n+ if (errp ||\n+ qemu_devtree_get_node_by_phandle(fdti->fdt,\n+ intc_node_path, intc_phandle)) {\n+ g_assert_not_reached();\n+ }\n+\n+ while (!fdt_init_has_opaque(fdti, intc_node_path)) {\n+ fdt_init_yield(fdti);\n+ }\n+\n+ intc = DEVICE(fdt_init_get_opaque(fdti, intc_node_path));\n+\n+ while (!intc->realized) {\n+ fdt_init_yield(fdti);\n+ }\n+\n+ return OBJECT(intc);\n+}\n+\n+static int armv8_timer_fdt_init(char *node_path, FDTMachineInfo *fdti,\n+ void *priv)\n+{\n+ Object *intc = fdt_armv8_timer_get_intc(fdti, node_path);\n+ CPUState *cpu;\n+ bool map_mode = false;\n+ qemu_irq *sec_irqs = NULL;\n+ qemu_irq *ns_irqs;\n+ qemu_irq *v_irqs;\n+ qemu_irq *h_irqs;\n+ uint32_t first_cpu_idx;\n+ uint32_t num_cpu;\n+ bool has_sec_ext;\n+ Error *err = NULL;\n+\n+ first_cpu_idx = object_property_get_uint(intc, \"first-cpu-idx\", &err);\n+ if (!err) {\n+ num_cpu = object_property_get_uint(intc, \"num-cpu\", &err);\n+ assert(!err);\n+ has_sec_ext = object_property_get_bool(intc, \"has-security-extensions\",\n+ &err);\n+ assert(!err);\n+ } else {\n+ /*\n+ * Connect all CPUs with the ARM_FEATURE_GENERIC_TIMER set for\n+ * backwards compatibility when the 'first-cpu-idx' property does not\n+ * exist.\n+ */\n+ num_cpu = 0;\n+ has_sec_ext = true;\n+ }\n+\n+ if (has_sec_ext) {\n+ sec_irqs = fdt_get_irq(fdti, node_path, 0, &map_mode);\n+ ns_irqs = fdt_get_irq(fdti, node_path, 1, &map_mode);\n+ v_irqs = fdt_get_irq(fdti, node_path, 2, &map_mode);\n+ h_irqs = fdt_get_irq(fdti, node_path, 3, &map_mode);\n+ } else {\n+ ns_irqs = fdt_get_irq(fdti, node_path, 0, &map_mode);\n+ v_irqs = fdt_get_irq(fdti, node_path, 1, &map_mode);\n+ h_irqs = fdt_get_irq(fdti, node_path, 2, &map_mode);\n+ }\n+\n+ assert(!map_mode); /* not supported for PPI */\n+\n+ for (cpu = first_cpu; cpu; cpu = CPU_NEXT(cpu)) {\n+ ARMCPU *acpu = ARM_CPU(cpu);\n+ bool is_gic_cpu;\n+\n+ if (!arm_feature(&acpu->env, ARM_FEATURE_GENERIC_TIMER)) {\n+ continue;\n+ }\n+\n+ is_gic_cpu = cpu->cpu_index >= first_cpu_idx &&\n+ cpu->cpu_index < (first_cpu_idx + num_cpu);\n+\n+ if (!num_cpu || is_gic_cpu) {\n+\n+ assert(*ns_irqs);\n+ assert(*v_irqs);\n+ assert(*h_irqs);\n+ qdev_connect_gpio_out(DEVICE(acpu), 0, *ns_irqs++);\n+ qdev_connect_gpio_out(DEVICE(acpu), 1, *v_irqs++);\n+ qdev_connect_gpio_out(DEVICE(acpu), 2, *h_irqs++);\n+\n+ if (has_sec_ext) {\n+ assert(*sec_irqs);\n+ qdev_connect_gpio_out(DEVICE(acpu), 3, *sec_irqs++);\n+ }\n+ }\n+ }\n+\n+ return 0;\n+}\n+\n+fdt_register_compatibility(armv8_timer_fdt_init,\n+ \"compatible:arm,armv8-timer\");\n+\n+#endif\n", "prefixes": [ "v2", "23/33" ] }