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GET /api/1.0/patches/2198177/?format=api
{ "id": 2198177, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2198177/?format=api", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.0/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<bmm.hfy4c1w8xq.gcc.gcc-TEST.why.135.2.3@forge-stage.sourceware.org>", "date": "2026-02-19T14:02:04", "name": "[v2,3/7,Vectorizer,Aarch64] : SLP MATCH Pattern: Add implementation for match / nmatch SVE instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a7bf6037b5dd3778508eda82152df17e88fbffb0", "submitter": { "id": 92460, "url": "http://patchwork.ozlabs.org/api/1.0/people/92460/?format=api", "name": "Andrei Tirziu via Sourceware Forge", "email": "forge-bot+why@forge-stage.sourceware.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/bmm.hfy4c1w8xq.gcc.gcc-TEST.why.135.2.3@forge-stage.sourceware.org/mbox/", "series": [ { "id": 492684, "url": "http://patchwork.ozlabs.org/api/1.0/series/492684/?format=api", "date": "2026-02-19T14:02:02", "name": "Vectorizer: New SLP Pattern", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492684/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2198177/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org; dmarc=none (p=none dis=none)\n header.from=forge-stage.sourceware.org", "sourceware.org;\n spf=pass smtp.mailfrom=forge-stage.sourceware.org", "server2.sourceware.org;\n arc=none smtp.remote-ip=38.145.34.39" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fGw7s4xKtz1xxQ\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 20 Feb 2026 01:03:05 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id A1F8C4B9DB52\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 19 Feb 2026 14:03:03 +0000 (GMT)", "from forge-stage.sourceware.org (vm08.sourceware.org [38.145.34.39])\n by sourceware.org (Postfix) with ESMTPS id E40D54B9DB4E\n for <gcc-patches@gcc.gnu.org>; Thu, 19 Feb 2026 14:02:36 +0000 (GMT)", "from forge-stage.sourceware.org (localhost [IPv6:::1])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256)\n (No client certificate requested)\n by forge-stage.sourceware.org (Postfix) with ESMTPS id A862344231;\n Thu, 19 Feb 2026 14:02:36 +0000 (UTC)" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org A1F8C4B9DB52", "OpenDKIM Filter v2.11.0 sourceware.org E40D54B9DB4E" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org E40D54B9DB4E", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org E40D54B9DB4E", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1771509757; cv=none;\n b=Qg7dSAL0xXYXv1BKT2DZFho6coLGL4xVQLLx1TnYDAJjZWquy/bdveXkFdsqmY4OMyq5nC9gJkZrFYJcd3cfwJKjHcm3dohUS6qPpDrbY1o3U25z8NCAb/Ffm1t6HV4m3Ir2v3XPx+tRdspGM3jijryNPPqIaEUUryCXkN1AyEw=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1771509757; c=relaxed/simple;\n bh=v7njFQ00sal8BIpl401gpgKtzSsmUhwl1oOptcCToWg=;\n h=From:Date:Subject:To:Message-ID;\n b=KoaU85o4pHFITZlWXrm/MvoNCzjJMkdE7UJsAKRDr318/h9fYDs/BV9mRO0l/RmW94+zgib5PbhlVDaUJrmDatGXNtR8KaS+7FhZN+SJYXYcGVNVZRFnDCeY/GS6MGreSikB5OMwxY8/72+G973ehsxh86omy78ldhCufxVRXfQ=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Andrei Tirziu via Sourceware Forge\n <forge-bot+why@forge-stage.sourceware.org>", "Date": "Thu, 19 Feb 2026 14:02:04 +0000", "Subject": "[PATCH v2 3/7] [Vectorizer][Aarch64]: SLP MATCH Pattern: Add\n implementation for match / nmatch SVE instructions", "To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>", "Cc": "Tamar Christina <tamar.christina@arm.com>,\n Victor Do Nascimento <victor.donascimento@arm.com>", "Message-ID": "\n <bmm.hfy4c1w8xq.gcc.gcc-TEST.why.135.2.3@forge-stage.sourceware.org>", "X-Mailer": "batrachomyomachia", "X-Pull-Request-Organization": "gcc", "X-Pull-Request-Repository": "gcc-TEST", "X-Pull-Request": "https://forge.sourceware.org/gcc/gcc-TEST/pulls/135", "References": "\n <bmm.hfy4c1w8xq.gcc.gcc-TEST.why.135.2.0@forge-stage.sourceware.org>", "In-Reply-To": "\n <bmm.hfy4c1w8xq.gcc.gcc-TEST.why.135.2.0@forge-stage.sourceware.org>", "X-Patch-URL": "\n https://forge.sourceware.org/why/gcc/commit/d5cec2a1672e0b22de93658c4dc33f00210270ad", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Reply-To": "gcc-patches mailing list <gcc-patches@gcc.gnu.org>,\n Tamar Christina <tamar.christina@arm.com>,\n Victor Do Nascimento <victor.donascimento@arm.com>,\n andreinichita.tirziu@arm.com", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "From: Andrei Nichita Tirziu <andreinichita.tirziu@arm.com>\n\nThe optabs introduced for the new MATCH Pattern need an implementation\nin the backend so that the vectorizer can complete the transformation.\n\nThe non-conditional optab is expanded to its conditional counterpart,\nusing an all-true predicate as a mask.\nThe conditional optab emits an SVE `match` or `nmatch` instructions.\n\nThe SVE backend doesn't make use of the `len` or `bias` arguments that\nthe conditional-len optab has, so there is no need to implement\nsuch a version.\n\ngcc/ChangeLog:\n\n\t* config/aarch64/aarch64-sve2.md: New patterns for match,\n\t\t\t\t\t nmatch optabs.\n\t* config/aarch64/iterators.md: New iterator for MATCH,\n\t\t\t\t NMATCH modes.\n---\n gcc/config/aarch64/aarch64-sve2.md | 70 ++++++++++++++++++++++++++++++\n gcc/config/aarch64/iterators.md | 3 ++\n 2 files changed, 73 insertions(+)", "diff": "diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md\nindex 4a2d2c1cb8ce..089216533625 100644\n--- a/gcc/config/aarch64/aarch64-sve2.md\n+++ b/gcc/config/aarch64/aarch64-sve2.md\n@@ -4333,6 +4333,76 @@\n ;; - NMATCH\n ;; -------------------------------------------------------------------------\n \n+;; SVE MATCH instruction. This is used by the `vec_match_any_from_optab`.\n+;;\n+;; The initial operands are (result, variants_vector, invariants_vector).\n+;; A full-true mask is generated to transform it into a valid instruction.\n+(define_expand \"@vec_match_any_from_<mode>\"\n+ [(set (match_operand:<VPRED> 0 \"register_operand\" \"=Upa\")\n+\t(unspec:<VPRED>\n+\t [(match_operand:SVE_MATCH_AND_NMATCH 1 \"register_operand\" \"w\")\n+\t (match_operand:SVE_MATCH_AND_NMATCH 2 \"register_operand\" \"w\")]\n+\t UNSPEC_MATCH))]\n+ \"TARGET_SVE2 && TARGET_NON_STREAMING\"\n+ {\n+ rtx true_pred = aarch64_ptrue_reg (<VPRED>mode);\n+ emit_insn (gen_vec_match_any_from_cond_<mode>\n+\t (operands[0], operands[1], operands[2], true_pred, operands[1]));\n+ DONE;\n+ }\n+)\n+\n+;; SVE MATCH instruction. This is used by the `cond_vec_match_any_from_optab`.\n+;;\n+;; The operands are\n+;; (result, variants_vector, invariants_vector, mask, ignored_vector).\n+(define_insn \"@vec_match_any_from_cond_<mode>\"\n+ [(set (match_operand:<VPRED> 0 \"register_operand\" \"=Upa\")\n+\t(unspec:<VPRED>\n+\t [(match_operand:SVE_MATCH_AND_NMATCH 1 \"register_operand\" \"w\")\n+\t (match_operand:SVE_MATCH_AND_NMATCH 2 \"register_operand\" \"w\")\n+\t (match_operand:<VPRED> 3 \"register_operand\" \"Upa\")\n+\t (match_operand:SVE_MATCH_AND_NMATCH 4 \"register_operand\" \"w\")]\n+\t UNSPEC_MATCH))]\n+ \"TARGET_SVE2 && TARGET_NON_STREAMING\"\n+ \"match\\t%0.<Vetype>, %3/z, %1.<Vetype>, %2.<Vetype>\"\n+)\n+\n+;; SVE NMATCH instruction. This is used by the `vec_match_none_from_optab`.\n+;;\n+;; The initial operands are (result, variants_vector, invariants_vector).\n+;; A full-true mask is generated to transform it into a valid instruction.\n+(define_expand \"@vec_match_none_from_<mode>\"\n+ [(set (match_operand:<VPRED> 0 \"register_operand\" \"=Upa\")\n+\t(unspec:<VPRED>\n+\t [(match_operand:SVE_MATCH_AND_NMATCH 1 \"register_operand\" \"w\")\n+\t (match_operand:SVE_MATCH_AND_NMATCH 2 \"register_operand\" \"w\")]\n+\t UNSPEC_NMATCH))]\n+ \"TARGET_SVE2 && TARGET_NON_STREAMING\"\n+ {\n+ rtx true_pred = aarch64_ptrue_reg (<VPRED>mode);\n+ emit_insn (gen_vec_match_none_from_cond_<mode>\n+\t (operands[0], operands[1], operands[2], true_pred, operands[1]));\n+ DONE;\n+ }\n+)\n+\n+;; SVE NMATCH instruction. This is used by the `cond_vec_match_none_from_optab`.\n+;;\n+;; The operands are\n+;; (result, variants_vector, invariants_vector, mask, ignored_vector).\n+(define_insn \"@vec_match_none_from_cond_<mode>\"\n+ [(set (match_operand:<VPRED> 0 \"register_operand\" \"=Upa\")\n+\t(unspec:<VPRED>\n+\t [(match_operand:SVE_MATCH_AND_NMATCH 1 \"register_operand\" \"w\")\n+\t (match_operand:SVE_MATCH_AND_NMATCH 2 \"register_operand\" \"w\")\n+\t (match_operand:<VPRED> 3 \"register_operand\" \"Upa\")\n+\t (match_operand:SVE_MATCH_AND_NMATCH 4 \"register_operand\" \"w\")]\n+\t UNSPEC_NMATCH))]\n+ \"TARGET_SVE2 && TARGET_NON_STREAMING\"\n+ \"nmatch\\t%0.<Vetype>, %3/z, %1.<Vetype>, %2.<Vetype>\"\n+)\n+\n ;; Predicated string matching.\n (define_insn \"@aarch64_pred_<sve_int_op><mode>\"\n [(set (match_operand:<VPRED> 0 \"register_operand\")\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex b425b0ed2ca3..d5c3073f153c 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -723,6 +723,9 @@\n ;; Used for narrowing SVE floating point operations.\n (define_mode_iterator VNx16F_NARROW [SVE_FULL_HFx2 VNx16SF])\n \n+;; SVE modes supported by MATCH and NMATCH instructions.\n+(define_mode_iterator SVE_MATCH_AND_NMATCH [VNx16QI VNx8HI])\n+\n ;; All SVE predicate modes.\n (define_mode_iterator PRED_ALL [VNx16BI VNx8BI VNx4BI VNx2BI])\n \n", "prefixes": [ "v2", "3/7", "Vectorizer", "Aarch64" ] }