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GET /api/1.0/patches/2198060/?format=api
{ "id": 2198060, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2198060/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260219090103.33697-4-skolothumtho@nvidia.com>", "date": "2026-02-19T09:01:01", "name": "[v7,3/5] hw/arm/smmuv3-accel: Allocate vEVENTQ for accelerated SMMUv3 devices", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "80d9ef8c8626bcc4d7f544aa26c11714821992de", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.0/people/91580/?format=api", "name": "Shameer Kolothum", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219090103.33697-4-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 492651, "url": "http://patchwork.ozlabs.org/api/1.0/series/492651/?format=api", "date": "2026-02-19T09:01:03", "name": "vEVENTQ support for accelerated SMMUv3 devices", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/492651/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2198060/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=NKo52WTo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail.nvidia.com; pr=C", "softfail client-ip=2a01:111:f403:c005::5;\n envelope-from=skolothumtho@nvidia.com;\n helo=CO1PR03CU002.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <nicolinc@nvidia.com>, <nathanc@nvidia.com>, <mochs@nvidia.com>,\n <jan@nvidia.com>, <jgg@nvidia.com>, <jonathan.cameron@huawei.com>,\n <zhangfei.gao@linaro.org>, <zhenzhong.duan@intel.com>, <kjaju@nvidia.com>,\n <skolothumtho@nvidia.com>", "Subject": "[PATCH v7 3/5] hw/arm/smmuv3-accel: Allocate vEVENTQ for accelerated\n SMMUv3 devices", "Date": "Thu, 19 Feb 2026 09:01:01 +0000", "Message-ID": "<20260219090103.33697-4-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260219090103.33697-1-skolothumtho@nvidia.com>", "References": "<20260219090103.33697-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SA2PEPF00003F67:EE_|DS0PR12MB8320:EE_", "X-MS-Office365-Filtering-Correlation-Id": "e9be039e-f279-4f64-0aff-08de6f9585eb", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|82310400026|376014|36860700013|1800799024;", "X-Microsoft-Antispam-Message-Info": "\n vWtdXeQizz7xn/t8ci+cdTBTJxvyHZ+94zsPfAspGXamiCjfRu8P2FtwanTjW9Zam5quqqYq91pWU5izU28NPUjFCm/wFuDO2mFloR4qQ4UNd2NoQXoB6AxuV4vM7oupoN88hektORKuCK8klOMDWT+Dd0O4CgXLHGHY2N5g0/j5YwJewYkAbNIED8EpaeLWdEKMUvmoKQM3jRnsOLfoJls55xNFtT8RK2zNfe1946V3bsAwqIEfL97clG2ggFPcXeu3YGYLgJ/FzwvOl0/SKO3rsShK3dHGsz3Io3t8XcaYadzkNlzwGjfnW8fZ6m8f5Ds6McNWI/7iS1tWfwkpjq7rIivqIqls3AjFHzhkRCqIBL1rwTAJm7zC5D1tNsF8OliY17CQjhm4QV4kJOPMNyJU3a7/fqlA2fqLpTz9zWMh8NzPzy0Sq1oYdmsqV+FYH4yJcJBOLb1+mFk0voBFu25Xhtegl12YkZ0bv1DDfM166fh2iMy4uL0Cp8qDNzJ1zjPLKSAzFDjFiME7wGDLmBxMYAJqJvNJrHBBxkYTa4R7bh4yULULyOT95/pcFi/fYoY4HgPu1FM+LujRkvsgSmWwhPGn4yoAN28XYM0L6qjcFLI/xmUpA9FaW7fu6oXHwAzZRsVMncq3UQ7Hab/zNrDz3rVcAmA/bYl+xWd8C4QECbVZxTPT1TAf4JcHlT1wRl6Z33KHg9Rn5OAeY+Jmyh+eLW6K3+lEzBMV4ce/+8weEl+j2NeqBCe3Ba0CZ1X8GCC6kZSc3hPV+D5n9KwiWlURT8PXrlw/vD21IJYL3aC8iyLxRb50qp07x9gVheiv7dQuVCzJJtdWl1LS6eYtTSIXarRJI6vLq0CAih11OQcn1mDtNQoX/C0qIAzz3UJi86yfpEaPf4pggVAy6ko2OCD18UFqpBJT7WsnNE5MqjdgtEkW/WFb6NLBel7r+wWHUVW4pkKabMbM/idtRV/83lZUCnygZMF15q8/hcOA56RO53dEAx8oDOJLKZqPFWTlM0iue0dcdEKIrVuSPPZcuRBIqNt3bKVXApoyqLa+h7g3Kkq9KjU1rWpZNT38D9Cgm+nAqYh8I7boR5gDfh6n0hkcSbsaf1iOa8aot8Urvg6Aqq3AHvR6I2MjfY3JalFQaIAAYYTWF9n8BFvRSt/QnLDAYxJZseW6Myb/m+9P7d30PcOs8PzoL3zBEpkyhRxSDDtkaR8ETcli0kSwlHxafGEokxbLxdMNwgjLGaPNZ2A39HByi1Yj7ZZDNaCGi7f+47/4PEMeWIj2MgrIOyUb82YRi1FCJFtkS4XjoHc9Jg04ooxf0yQ5LTJLJBXr5Ae2wvlPyR3MmJ1h/1oTiQH52ZvSgZhRobEuOy5yr7iprvrrr5fKwxFf8IiGzjg8ivJHPJzef1FFhT92vqGRuv5nLwVW4Ousob4h4E8qT0ioUkEDsJ+0uNYEl8fjotj6gPdW2G6Tjy0wUM05znpmOLESMWXQYeg+zaP/xkWFvopWAkc3Q+2GSFfpNeHqkQuYsEVv3JQ7DHzecgVvyjNX4KNsgLQXe+ftMLI7xN0o1m5opZN/tqKavOp55BCAO6AV35VWqzhdLm3jCAECuFlWDXAJapR5L9mKK31wu7OL7f2xwqP3BmdF3CdDdwuzhEqHZdtJqcL+vOnUy1RnXa8Vm7WU3g==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SA2PEPF00003F67.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS0PR12MB8320", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.043,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Nicolin Chen <nicolinc@nvidia.com>\n\nWhen the guest enables the Event Queue and a vIOMMU is present, allocate a\nvEVENTQ object so that host-side events related to the vIOMMU can be\nreceived and propagated back to the guest.\n\nFor cold-plugged devices using SMMUv3 acceleration, the vIOMMU is created\nbefore the guest boots. In this case, the vEVENTQ is allocated when the\nguest writes to SMMU_CR0 and sets EVENTQEN = 1.\n\nIf no cold-plugged device exists at boot (i.e. no vIOMMU initially), the\nvEVENTQ is allocated when a vIOMMU is created, i.e. during the first\ndevice hot-plug.\n\nErrors from command queue consumption and vEVENTQ allocation are reported\nindependently as the two operations are unrelated.\n\nEvent read and propagation will be added in a later patch.\n\nSigned-off-by: Nicolin Chen <nicolinc@nvidia.com>\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nTested-by: Nicolin Chen <nicolinc@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/smmuv3-accel.h | 6 +++++\n hw/arm/smmuv3-accel.c | 61 +++++++++++++++++++++++++++++++++++++++++--\n hw/arm/smmuv3.c | 6 +++++\n 3 files changed, 71 insertions(+), 2 deletions(-)", "diff": "diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h\nindex a8a64802ec..dba6c71de5 100644\n--- a/hw/arm/smmuv3-accel.h\n+++ b/hw/arm/smmuv3-accel.h\n@@ -22,6 +22,7 @@\n */\n typedef struct SMMUv3AccelState {\n IOMMUFDViommu *viommu;\n+ IOMMUFDVeventq *veventq;\n uint32_t bypass_hwpt_id;\n uint32_t abort_hwpt_id;\n QLIST_HEAD(, SMMUv3AccelDevice) device_list;\n@@ -50,6 +51,7 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp);\n bool smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,\n Error **errp);\n void smmuv3_accel_idr_override(SMMUv3State *s);\n+bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp);\n void smmuv3_accel_reset(SMMUv3State *s);\n #else\n static inline void smmuv3_accel_init(SMMUv3State *s)\n@@ -80,6 +82,10 @@ smmuv3_accel_issue_inv_cmd(SMMUv3State *s, void *cmd, SMMUDevice *sdev,\n static inline void smmuv3_accel_idr_override(SMMUv3State *s)\n {\n }\n+static inline bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n+{\n+ return true;\n+}\n static inline void smmuv3_accel_reset(SMMUv3State *s)\n {\n }\ndiff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex c19c526fca..f703ea1aac 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -390,6 +390,19 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void *cmd, SMMUDevice *sdev,\n sizeof(Cmd), &entry_num, cmd, errp);\n }\n \n+static void smmuv3_accel_free_veventq(SMMUv3AccelState *accel)\n+{\n+ IOMMUFDVeventq *veventq = accel->veventq;\n+\n+ if (!veventq) {\n+ return;\n+ }\n+ close(veventq->veventq_fd);\n+ iommufd_backend_free_id(accel->viommu->iommufd, veventq->veventq_id);\n+ g_free(veventq);\n+ accel->veventq = NULL;\n+}\n+\n static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n {\n IOMMUFDViommu *viommu = accel->viommu;\n@@ -397,6 +410,7 @@ static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n if (!viommu) {\n return;\n }\n+ smmuv3_accel_free_veventq(accel);\n iommufd_backend_free_id(viommu->iommufd, accel->bypass_hwpt_id);\n iommufd_backend_free_id(viommu->iommufd, accel->abort_hwpt_id);\n iommufd_backend_free_id(viommu->iommufd, accel->viommu->viommu_id);\n@@ -404,6 +418,41 @@ static void smmuv3_accel_free_viommu(SMMUv3AccelState *accel)\n accel->viommu = NULL;\n }\n \n+bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n+{\n+ SMMUv3AccelState *accel = s->s_accel;\n+ IOMMUFDVeventq *veventq;\n+ uint32_t veventq_id;\n+ uint32_t veventq_fd;\n+\n+ if (!accel || !accel->viommu) {\n+ return true;\n+ }\n+\n+ if (accel->veventq) {\n+ return true;\n+ }\n+\n+ if (!smmuv3_eventq_enabled(s)) {\n+ return true;\n+ }\n+\n+ if (!iommufd_backend_alloc_veventq(accel->viommu->iommufd,\n+ accel->viommu->viommu_id,\n+ IOMMU_VEVENTQ_TYPE_ARM_SMMUV3,\n+ 1 << s->eventq.log2size, &veventq_id,\n+ &veventq_fd, errp)) {\n+ return false;\n+ }\n+\n+ veventq = g_new0(IOMMUFDVeventq, 1);\n+ veventq->veventq_id = veventq_id;\n+ veventq->veventq_fd = veventq_fd;\n+ veventq->viommu = accel->viommu;\n+ accel->veventq = veventq;\n+ return true;\n+}\n+\n static bool\n smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n Error **errp)\n@@ -429,6 +478,7 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n viommu->viommu_id = viommu_id;\n viommu->s2_hwpt_id = s2_hwpt_id;\n viommu->iommufd = idev->iommufd;\n+ accel->viommu = viommu;\n \n /*\n * Pre-allocate HWPTs for S1 bypass and abort cases. These will be attached\n@@ -448,14 +498,20 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n goto free_abort_hwpt;\n }\n \n+ /* Allocate a vEVENTQ if guest has enabled event queue */\n+ if (!smmuv3_accel_alloc_veventq(s, errp)) {\n+ goto free_bypass_hwpt;\n+ }\n+\n /* Attach a HWPT based on SMMUv3 GBPA.ABORT value */\n hwpt_id = smmuv3_accel_gbpa_hwpt(s, accel);\n if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) {\n- goto free_bypass_hwpt;\n+ goto free_veventq;\n }\n- accel->viommu = viommu;\n return true;\n \n+free_veventq:\n+ smmuv3_accel_free_veventq(accel);\n free_bypass_hwpt:\n iommufd_backend_free_id(idev->iommufd, accel->bypass_hwpt_id);\n free_abort_hwpt:\n@@ -463,6 +519,7 @@ free_abort_hwpt:\n free_viommu:\n iommufd_backend_free_id(idev->iommufd, viommu->viommu_id);\n g_free(viommu);\n+ accel->viommu = NULL;\n return false;\n }\n \ndiff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c\nindex c08d58c579..5d718da764 100644\n--- a/hw/arm/smmuv3.c\n+++ b/hw/arm/smmuv3.c\n@@ -1605,6 +1605,12 @@ static MemTxResult smmu_writel(SMMUv3State *s, hwaddr offset,\n s->cr0ack = data & ~SMMU_CR0_RESERVED;\n /* in case the command queue has been enabled */\n smmuv3_cmdq_consume(s, &local_err);\n+ if (local_err) {\n+ error_report_err(local_err);\n+ local_err = NULL;\n+ }\n+ /* Allocate vEVENTQ if EVENTQ is enabled and a vIOMMU is available */\n+ smmuv3_accel_alloc_veventq(s, &local_err);\n break;\n case A_CR1:\n s->cr[1] = data;\n", "prefixes": [ "v7", "3/5" ] }