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GET /api/1.0/patches/2198056/?format=api
{ "id": 2198056, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2198056/?format=api", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.0/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260219090103.33697-6-skolothumtho@nvidia.com>", "date": "2026-02-19T09:01:03", "name": "[v7,5/5] hw/arm/smmuv3-accel: Read and propagate host vIOMMU events", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "907df1ee63730c474e9ba3d64817b482bae25f42", "submitter": { "id": 91580, "url": "http://patchwork.ozlabs.org/api/1.0/people/91580/?format=api", "name": "Shameer Kolothum", "email": "skolothumtho@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260219090103.33697-6-skolothumtho@nvidia.com/mbox/", "series": [ { "id": 492651, "url": "http://patchwork.ozlabs.org/api/1.0/series/492651/?format=api", "date": "2026-02-19T09:01:03", "name": "vEVENTQ support for accelerated SMMUv3 devices", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/492651/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2198056/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=PISvcij3;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], 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helo=BL2PR02CU003.outbound.protection.outlook.com" ], "From": "Shameer Kolothum <skolothumtho@nvidia.com>", "To": "<qemu-arm@nongnu.org>, <qemu-devel@nongnu.org>", "CC": "<eric.auger@redhat.com>, <peter.maydell@linaro.org>,\n <nicolinc@nvidia.com>, <nathanc@nvidia.com>, <mochs@nvidia.com>,\n <jan@nvidia.com>, <jgg@nvidia.com>, <jonathan.cameron@huawei.com>,\n <zhangfei.gao@linaro.org>, <zhenzhong.duan@intel.com>, <kjaju@nvidia.com>,\n <skolothumtho@nvidia.com>", "Subject": "[PATCH v7 5/5] hw/arm/smmuv3-accel: Read and propagate host vIOMMU\n events", "Date": "Thu, 19 Feb 2026 09:01:03 +0000", "Message-ID": "<20260219090103.33697-6-skolothumtho@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260219090103.33697-1-skolothumtho@nvidia.com>", "References": "<20260219090103.33697-1-skolothumtho@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": 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002eb52e-413c-459f-d162-08de6f958a34", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SA2PEPF00003F67.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH8PR12MB9744", "X-Spam_score_int": "-10", "X-Spam_score": "-1.1", "X-Spam_bar": "-", "X-Spam_report": "(-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.043,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001,\n SPF_NONE=0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Install an event handler on the vEVENTQ fd to read and propagate host\ngenerated vIOMMU events to the guest.\n\nThe handler runs in QEMU's main loop, using a non-blocking fd registered\nvia qemu_set_fd_handler().\n\nReviewed-by: Eric Auger <eric.auger@redhat.com>\nReviewed-by: Nicolin Chen <nicolinc@nvidia.com>\nTested-by: Nicolin Chen <nicolinc@nvidia.com>\nSigned-off-by: Shameer Kolothum <skolothumtho@nvidia.com>\n---\n hw/arm/smmuv3-accel.c | 64 +++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 64 insertions(+)", "diff": "diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex f703ea1aac..17306cd04b 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -390,6 +390,50 @@ bool smmuv3_accel_issue_inv_cmd(SMMUv3State *bs, void *cmd, SMMUDevice *sdev,\n sizeof(Cmd), &entry_num, cmd, errp);\n }\n \n+static void smmuv3_accel_event_read(void *opaque)\n+{\n+ SMMUv3State *s = opaque;\n+ IOMMUFDVeventq *veventq = s->s_accel->veventq;\n+ struct {\n+ struct iommufd_vevent_header hdr;\n+ struct iommu_vevent_arm_smmuv3 vevent;\n+ } buf;\n+ enum iommu_veventq_type type = IOMMU_VEVENTQ_TYPE_ARM_SMMUV3;\n+ uint32_t id = veventq->veventq_id;\n+ uint32_t last_seq = veventq->last_event_seq;\n+ ssize_t bytes;\n+\n+ bytes = read(veventq->veventq_fd, &buf, sizeof(buf));\n+ if (bytes <= 0) {\n+ if (errno == EAGAIN || errno == EINTR) {\n+ return;\n+ }\n+ error_report_once(\"vEVENTQ(type %u id %u): read failed (%m)\", type, id);\n+ return;\n+ }\n+\n+ if (bytes == sizeof(buf.hdr) &&\n+ (buf.hdr.flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS)) {\n+ error_report_once(\"vEVENTQ(type %u id %u): overflowed\", type, id);\n+ veventq->event_start = false;\n+ return;\n+ }\n+ if (bytes < sizeof(buf)) {\n+ error_report_once(\"vEVENTQ(type %u id %u): short read(%zd/%zd bytes)\",\n+ type, id, bytes, sizeof(buf));\n+ return;\n+ }\n+\n+ /* Check sequence in hdr for lost events if any */\n+ if (veventq->event_start && (buf.hdr.sequence - last_seq != 1)) {\n+ error_report_once(\"vEVENTQ(type %u id %u): lost %u event(s)\",\n+ type, id, buf.hdr.sequence - last_seq - 1);\n+ }\n+ veventq->last_event_seq = buf.hdr.sequence;\n+ veventq->event_start = true;\n+ smmuv3_propagate_event(s, (Evt *)&buf.vevent);\n+}\n+\n static void smmuv3_accel_free_veventq(SMMUv3AccelState *accel)\n {\n IOMMUFDVeventq *veventq = accel->veventq;\n@@ -397,6 +441,7 @@ static void smmuv3_accel_free_veventq(SMMUv3AccelState *accel)\n if (!veventq) {\n return;\n }\n+ qemu_set_fd_handler(veventq->veventq_fd, NULL, NULL, NULL);\n close(veventq->veventq_fd);\n iommufd_backend_free_id(accel->viommu->iommufd, veventq->veventq_id);\n g_free(veventq);\n@@ -424,6 +469,7 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n IOMMUFDVeventq *veventq;\n uint32_t veventq_id;\n uint32_t veventq_fd;\n+ int flags;\n \n if (!accel || !accel->viommu) {\n return true;\n@@ -445,12 +491,30 @@ bool smmuv3_accel_alloc_veventq(SMMUv3State *s, Error **errp)\n return false;\n }\n \n+ flags = fcntl(veventq_fd, F_GETFL);\n+ if (flags < 0) {\n+ error_setg_errno(errp, errno, \"Failed to get flags for vEVENTQ fd\");\n+ goto free_veventq;\n+ }\n+ if (fcntl(veventq_fd, F_SETFL, flags | O_NONBLOCK) < 0) {\n+ error_setg_errno(errp, errno, \"Failed to set O_NONBLOCK on vEVENTQ fd\");\n+ goto free_veventq;\n+ }\n+\n veventq = g_new0(IOMMUFDVeventq, 1);\n veventq->veventq_id = veventq_id;\n veventq->veventq_fd = veventq_fd;\n veventq->viommu = accel->viommu;\n accel->veventq = veventq;\n+\n+ /* Set up event handler for veventq fd */\n+ qemu_set_fd_handler(veventq_fd, smmuv3_accel_event_read, NULL, s);\n return true;\n+\n+free_veventq:\n+ close(veventq_fd);\n+ iommufd_backend_free_id(accel->viommu->iommufd, veventq_id);\n+ return false;\n }\n \n static bool\n", "prefixes": [ "v7", "5/5" ] }