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GET /api/1.0/patches/2197803/?format=api
{ "id": 2197803, "url": "http://patchwork.ozlabs.org/api/1.0/patches/2197803/?format=api", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.0/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260218145809.1622856-6-bwicaksono@nvidia.com>", "date": "2026-02-18T14:58:06", "name": "[v2,5/8] perf/arm_cspmu: nvidia: Add Tegra410 PCIE-TGT PMU", "commit_ref": null, "pull_url": null, "state": "handled-elsewhere", "archived": false, "hash": "ed1e0be8dd6f44b6c1101ba07b4b3f7389eac94d", "submitter": { "id": 83903, "url": "http://patchwork.ozlabs.org/api/1.0/people/83903/?format=api", "name": "Besar Wicaksono", "email": "bwicaksono@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260218145809.1622856-6-bwicaksono@nvidia.com/mbox/", "series": [ { "id": 492565, "url": "http://patchwork.ozlabs.org/api/1.0/series/492565/?format=api", "date": "2026-02-18T14:58:01", "name": "perf: add NVIDIA Tegra410 Uncore PMU support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/492565/mbox/" } ], "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2197803/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-12057-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=dLR+BYu2;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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pr=C", "From": "Besar Wicaksono <bwicaksono@nvidia.com>", "To": "<will@kernel.org>, <suzuki.poulose@arm.com>, <robin.murphy@arm.com>,\n\t<ilkka@os.amperecomputing.com>", "CC": "<linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, <mark.rutland@arm.com>, <treding@nvidia.com>,\n\t<jonathanh@nvidia.com>, <vsethi@nvidia.com>, <rwiley@nvidia.com>,\n\t<sdonthineni@nvidia.com>, <skelley@nvidia.com>, <ywan@nvidia.com>,\n\t<mochs@nvidia.com>, <nirmoyd@nvidia.com>, Besar Wicaksono\n\t<bwicaksono@nvidia.com>", "Subject": "[PATCH v2 5/8] perf/arm_cspmu: nvidia: Add Tegra410 PCIE-TGT PMU", "Date": "Wed, 18 Feb 2026 14:58:06 +0000", "Message-ID": "<20260218145809.1622856-6-bwicaksono@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260218145809.1622856-1-bwicaksono@nvidia.com>", "References": "<20260218145809.1622856-1-bwicaksono@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A103:EE_|DM6PR12MB4467:EE_", "X-MS-Office365-Filtering-Correlation-Id": "111ca0b9-aec8-43ec-67bf-08de6efe4373", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024;", "X-Microsoft-Antispam-Message-Info": "\n 7Ky6xuvuv61p4MBXUy3g3WmBvA2ch3KsS4nn+yR3r0uOnMjf5PczTxeDV3t9O+xwhMC0KqFnvvhCZsg0BmjzBlFZ98SVoOlFfOQi6Eh5wLLlMZyDL3MXKy7WtwsXhYmj03oyZMVVVb68zHNH5DoEqMKismLZoLYWcZXhRCQqJjwPuxMoZ42nLndLjiIV4DZ0cols5/tNxCGAE4JmPBx2/U/mYfzMQP5KBzMQK6P2il4o0rvkkM4s1SU2OsLpeQEkaZsarurvaOWnMV5Eqm5ysPhPy64Ikqa906t6NXipi6jLHyC9T9Mitl12R++S/Bc88BOgh51VmRCfP9MCXjaBzQgp+sgE7mEed4u0xTy1cx8QNcFIIRy9JUW9l7h+hm8COEXc+rogSMuBfdIpZ3d5Pcntv3PNE+QSD2VJyZHXO+Q5QsjtsKFV/RhyA0Dgw8WqxXwHegXaaj/ohtCHSpLL65WISyErLK/GfmdJ8/FfJV55btPHZG40MpZjb/rja5zCP3rxlYwwVFjTQC12gYjLbWH5Lhspa69/bci485HvhQF8ZBymFa/GFPOFBFSt5+KdQJ42MqqLvi+QOdBwgT0qgSW/1MHfyE+slz9W9axAjZ2fNyu0MWybZRiuVTQyONIlxJzOEI9GP/7/yzMl5MIVpZ2CtRDR0bU3Y9gYdwmA0CtSOn2XZB/goezVAretVc0bA8dCPcfJhXolG0Qk4m2+c8p1bUusk8t2SYvPGUlItoVYJR8zvs5j97d0Ds36ZsCYMdkdY9KORWPnt8BlbXSDbdKE1WdLTwalGlpbT7W+Mh6pNw+C1cFCavJADpgxsjh58StEsWZa/uH+ErGEGGRizqIOt+3sDHq77bVh/CZOvwq0i3du4pPgYiU4alj6XVNOHZfGFF08mjyjR84XLaq1Qlr5h0klLMwk721I2hxWSiRkYheTPuSViWSWSXD/VXfTkkYkfRNrFuSSFiNV/pFPq+Psa3/kghKmbY0dh1O9VOdM7SXrnxcZdbguWvtjPWCQ91x1SPHN+Ty3d26/hRB9BiIVnMpS4DPa/vYqiWAnntHAWf1RPkki2R82XV0599d8G7KfIaii/4UmPHa/stcJoVvsXhOuvS+SrHqAbw1J8QeZNm1ihx2Fg2qsOO08ZyUJPn6/ICwsYMTSvJN3dAR5N+8oKblTvSKKc9ksO+eJX6YLHCl14P1J93f+d+DlPTOH4JJLKkzgCg3otqBbypJTbGgavYmuJroaFZd81ZII29+Usl9e/Djazop1mBcaoCzV+rQpJZNlyatddSnVUNa22rkNYJBFzBBNOgH6RZJZxce1w0/lMKhZyB1Nr7tfZ8ElL/9Uafzt5DE/CXNrs4ApJzpgQgEi4ifosz/jNdlUbeO57itb9mdNcSHKSJfOV8JXFFFFNrzVODx/eC3YrUoE9wQBdO9cTfq+XehjbF5Ph91zsqBPk24irq8R0pXrpdlwfU9ef0MGStlKbqcOLZZBMcSgWGnktdnPDyo6P7TMMZMpqHs1wEnrS1/DcSfhodRL9ubBPIliqzOUsx5TdRUJNdPlB6T2s0ZCIFN/8jGWJ9vxMi0byda+u9fv6SFqWq/+oTkAJyWvbEU9XstmKvvivxTDrZ1vbvSJ0aUf/lqpGcosIvhZFVVOk01n7mx412Ul2Ma3dSAK2ahoguq+Kj5tRQ==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tyJh/DRKdIEGRp+k1ItcgzO59NB6AUN604xV9B5dOVkd8xSOZK/VlTEOuItF2+G3+wyKH0X/ki0qHcezDKLR8JvUwIC0ED1vbedFp+r2cemM0Sha6tkt9S0JkbsFE+Mgyf49qhK0srEgCaIItx0+81n1awmtyWY5E+yj70/DLIVAblZ61/9FqGfAXshezhIblNIFRPmDg9UJWVmbPZt3IXbu2f/BhvUoUdQmEutW2+Q8DJN0+8D6OUkw+ttwQ8PLBNzHvGtbxunTvKP5MQ8uYYFDzC4HUcJ1zCpdkjI/bUpkPcZQmU2pHoE9ehqe3nZoIPWGAkEcYsQRK/dktFRjzTvywbmPsMnv4tUQJ5FzbIHNfkbX7bJ5/S3yJhZs0UPS3Ock0phAq1w8Tot5DMwKhb/CVemC8PhwxzyFMN+Vz1vin4M0UQP32q6UcqWKa4sMG", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Feb 2026 14:59:06.3704\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 111ca0b9-aec8-43ec-67bf-08de6efe4373", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL02EPF0001A103.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM6PR12MB4467" }, "content": "Adds PCIE-TGT PMU support in Tegra410 SOC. This PMU is\ninstanced in each root complex in the SOC and it captures\ntraffic originating from any source towards PCIE BAR and CXL\nHDM range. The traffic can be filtered based on the\ndestination root port or target address range.\n\nReviewed-by: Ilkka Koskinen <ilkka@os.amperecomputing.com>\nSigned-off-by: Besar Wicaksono <bwicaksono@nvidia.com>\n---\n .../admin-guide/perf/nvidia-tegra410-pmu.rst | 76 +++++\n drivers/perf/arm_cspmu/nvidia_cspmu.c | 323 ++++++++++++++++++\n 2 files changed, 399 insertions(+)", "diff": "diff --git a/Documentation/admin-guide/perf/nvidia-tegra410-pmu.rst b/Documentation/admin-guide/perf/nvidia-tegra410-pmu.rst\nindex 8528685ddb61..07dc447eead7 100644\n--- a/Documentation/admin-guide/perf/nvidia-tegra410-pmu.rst\n+++ b/Documentation/admin-guide/perf/nvidia-tegra410-pmu.rst\n@@ -7,6 +7,7 @@ metrics like memory bandwidth, latency, and utilization:\n \n * Unified Coherence Fabric (UCF)\n * PCIE\n+* PCIE-TGT\n \n PMU Driver\n ----------\n@@ -211,6 +212,11 @@ Example usage:\n \n perf stat -a -e nvidia_pcie_pmu_0_rc_4/event=0x4,src_bdf=0x0180,src_bdf_en=0x1/\n \n+.. _NVIDIA_T410_PCIE_PMU_RC_Mapping_Section:\n+\n+Mapping the RC# to lspci segment number\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n Mapping the RC# to lspci segment number can be non-trivial; hence a new NVIDIA\n Designated Vendor Specific Capability (DVSEC) register is added into the PCIE config space\n for each RP. This DVSEC has vendor id \"10de\" and DVSEC id of \"0x4\". The DVSEC register\n@@ -266,3 +272,73 @@ Example output::\n 000d:40:00.0: Bus=40, Segment=0d, RP=01, RC=04, Socket=01\n 000d:c0:00.0: Bus=c0, Segment=0d, RP=02, RC=04, Socket=01\n 000e:00:00.0: Bus=00, Segment=0e, RP=00, RC=05, Socket=01\n+\n+PCIE-TGT PMU\n+------------\n+\n+The PCIE-TGT PMU monitors traffic targeting PCIE BAR and CXL HDM ranges.\n+There is one PCIE-TGT PMU per PCIE root complex (RC) in the SoC. Each RC in\n+Tegra410 SoC can have up to 16 lanes that can be bifurcated into up to 8 root\n+ports (RP). The PMU provides RP filter to count PCIE BAR traffic to each RP and\n+address filter to count access to PCIE BAR or CXL HDM ranges. The details\n+of the filters are described in the following sections.\n+\n+Mapping the RC# to lspci segment number is similar to the PCIE PMU.\n+Please see :ref:`NVIDIA_T410_PCIE_PMU_RC_Mapping_Section` for more info.\n+\n+The events and configuration options of this PMU device are available in sysfs,\n+see /sys/bus/event_source/devices/nvidia_pcie_tgt_pmu_<socket-id>_rc_<pcie-rc-id>.\n+\n+The events in this PMU can be used to measure bandwidth and utilization:\n+\n+ * rd_req: count the number of read requests to PCIE.\n+ * wr_req: count the number of write requests to PCIE.\n+ * rd_bytes: count the number of bytes transferred by rd_req.\n+ * wr_bytes: count the number of bytes transferred by wr_req.\n+ * cycles: counts the PCIE cycles.\n+\n+The average bandwidth is calculated as::\n+\n+ AVG_RD_BANDWIDTH_IN_GBPS = RD_BYTES / ELAPSED_TIME_IN_NS\n+ AVG_WR_BANDWIDTH_IN_GBPS = WR_BYTES / ELAPSED_TIME_IN_NS\n+\n+The average request rate is calculated as::\n+\n+ AVG_RD_REQUEST_RATE = RD_REQ / CYCLES\n+ AVG_WR_REQUEST_RATE = WR_REQ / CYCLES\n+\n+The PMU events can be filtered based on the destination root port or target\n+address range. Filtering based on RP is only available for PCIE BAR traffic.\n+Address filter works for both PCIE BAR and CXL HDM ranges. These filters can be\n+found in sysfs, see\n+/sys/bus/event_source/devices/nvidia_pcie_tgt_pmu_<socket-id>_rc_<pcie-rc-id>/format/.\n+\n+Destination filter settings:\n+\n+* dst_rp_mask: bitmask to select the root port(s) to monitor. E.g. \"dst_rp_mask=0xFF\"\n+ corresponds to all root ports (from 0 to 7) in the PCIE RC. Note that this filter is\n+ only available for PCIE BAR traffic.\n+* dst_addr_base: BAR or CXL HDM filter base address.\n+* dst_addr_mask: BAR or CXL HDM filter address mask.\n+* dst_addr_en: enable BAR or CXL HDM address range filter. If this is set, the\n+ address range specified by \"dst_addr_base\" and \"dst_addr_mask\" will be used to filter\n+ the PCIE BAR and CXL HDM traffic address. The PMU uses the following comparison\n+ to determine if the traffic destination address falls within the filter range::\n+\n+ (txn's addr & dst_addr_mask) == (dst_addr_base & dst_addr_mask)\n+\n+ If the comparison succeeds, then the event will be counted.\n+\n+If the destination filter is not specified, the RP filter will be configured by default\n+to count PCIE BAR traffic to all root ports.\n+\n+Example usage:\n+\n+* Count event id 0x0 to root port 0 and 1 of PCIE RC-0 on socket 0::\n+\n+ perf stat -a -e nvidia_pcie_tgt_pmu_0_rc_0/event=0x0,dst_rp_mask=0x3/\n+\n+* Count event id 0x1 for accesses to PCIE BAR or CXL HDM address range\n+ 0x10000 to 0x100FF on socket 0's PCIE RC-1::\n+\n+ perf stat -a -e nvidia_pcie_tgt_pmu_0_rc_1/event=0x1,dst_addr_base=0x10000,dst_addr_mask=0xFFF00,dst_addr_en=0x1/\ndiff --git a/drivers/perf/arm_cspmu/nvidia_cspmu.c b/drivers/perf/arm_cspmu/nvidia_cspmu.c\nindex 42f11f37bddf..25c408b56dc8 100644\n--- a/drivers/perf/arm_cspmu/nvidia_cspmu.c\n+++ b/drivers/perf/arm_cspmu/nvidia_cspmu.c\n@@ -42,6 +42,24 @@\n #define NV_PCIE_V2_FILTER2_DST GENMASK_ULL(NV_PCIE_V2_DST_COUNT - 1, 0)\n #define NV_PCIE_V2_FILTER2_DEFAULT NV_PCIE_V2_FILTER2_DST\n \n+#define NV_PCIE_TGT_PORT_COUNT 8ULL\n+#define NV_PCIE_TGT_EV_TYPE_CC 0x4\n+#define NV_PCIE_TGT_EV_TYPE_COUNT 3ULL\n+#define NV_PCIE_TGT_EV_TYPE_MASK GENMASK_ULL(NV_PCIE_TGT_EV_TYPE_COUNT - 1, 0)\n+#define NV_PCIE_TGT_FILTER2_MASK GENMASK_ULL(NV_PCIE_TGT_PORT_COUNT, 0)\n+#define NV_PCIE_TGT_FILTER2_PORT GENMASK_ULL(NV_PCIE_TGT_PORT_COUNT - 1, 0)\n+#define NV_PCIE_TGT_FILTER2_ADDR_EN BIT(NV_PCIE_TGT_PORT_COUNT)\n+#define NV_PCIE_TGT_FILTER2_ADDR GENMASK_ULL(15, NV_PCIE_TGT_PORT_COUNT)\n+#define NV_PCIE_TGT_FILTER2_DEFAULT NV_PCIE_TGT_FILTER2_PORT\n+\n+#define NV_PCIE_TGT_ADDR_COUNT 8ULL\n+#define NV_PCIE_TGT_ADDR_STRIDE 20\n+#define NV_PCIE_TGT_ADDR_CTRL 0xD38\n+#define NV_PCIE_TGT_ADDR_BASE_LO 0xD3C\n+#define NV_PCIE_TGT_ADDR_BASE_HI 0xD40\n+#define NV_PCIE_TGT_ADDR_MASK_LO 0xD44\n+#define NV_PCIE_TGT_ADDR_MASK_HI 0xD48\n+\n #define NV_GENERIC_FILTER_ID_MASK GENMASK_ULL(31, 0)\n \n #define NV_PRODID_MASK\t(PMIIDR_PRODUCTID | PMIIDR_VARIANT | PMIIDR_REVISION)\n@@ -186,6 +204,15 @@ static struct attribute *pcie_v2_pmu_event_attrs[] = {\n \tNULL,\n };\n \n+static struct attribute *pcie_tgt_pmu_event_attrs[] = {\n+\tARM_CSPMU_EVENT_ATTR(rd_bytes,\t\t0x0),\n+\tARM_CSPMU_EVENT_ATTR(wr_bytes,\t\t0x1),\n+\tARM_CSPMU_EVENT_ATTR(rd_req,\t\t0x2),\n+\tARM_CSPMU_EVENT_ATTR(wr_req,\t\t0x3),\n+\tARM_CSPMU_EVENT_ATTR(cycles, NV_PCIE_TGT_EV_TYPE_CC),\n+\tNULL,\n+};\n+\n static struct attribute *generic_pmu_event_attrs[] = {\n \tARM_CSPMU_EVENT_ATTR(cycles, ARM_CSPMU_EVT_CYCLES_DEFAULT),\n \tNULL,\n@@ -239,6 +266,15 @@ static struct attribute *pcie_v2_pmu_format_attrs[] = {\n \tNULL,\n };\n \n+static struct attribute *pcie_tgt_pmu_format_attrs[] = {\n+\tARM_CSPMU_FORMAT_ATTR(event, \"config:0-2\"),\n+\tARM_CSPMU_FORMAT_ATTR(dst_rp_mask, \"config:3-10\"),\n+\tARM_CSPMU_FORMAT_ATTR(dst_addr_en, \"config:11\"),\n+\tARM_CSPMU_FORMAT_ATTR(dst_addr_base, \"config1:0-63\"),\n+\tARM_CSPMU_FORMAT_ATTR(dst_addr_mask, \"config2:0-63\"),\n+\tNULL,\n+};\n+\n static struct attribute *generic_pmu_format_attrs[] = {\n \tARM_CSPMU_FORMAT_EVENT_ATTR,\n \tARM_CSPMU_FORMAT_FILTER_ATTR,\n@@ -478,6 +514,267 @@ static int pcie_v2_pmu_validate_event(struct arm_cspmu *cspmu,\n \treturn 0;\n }\n \n+struct pcie_tgt_addr_filter {\n+\tu32 refcount;\n+\tu64 base;\n+\tu64 mask;\n+};\n+\n+struct pcie_tgt_data {\n+\tstruct pcie_tgt_addr_filter addr_filter[NV_PCIE_TGT_ADDR_COUNT];\n+\tvoid __iomem *addr_filter_reg;\n+};\n+\n+#if defined(CONFIG_ACPI)\n+static int pcie_tgt_init_data(struct arm_cspmu *cspmu)\n+{\n+\tint ret;\n+\tstruct acpi_device *adev;\n+\tstruct pcie_tgt_data *data;\n+\tstruct list_head resource_list;\n+\tstruct resource_entry *rentry;\n+\tstruct nv_cspmu_ctx *ctx = to_nv_cspmu_ctx(cspmu);\n+\tstruct device *dev = cspmu->dev;\n+\n+\tdata = devm_kzalloc(dev, sizeof(struct pcie_tgt_data), GFP_KERNEL);\n+\tif (!data)\n+\t\treturn -ENOMEM;\n+\n+\tadev = arm_cspmu_acpi_dev_get(cspmu);\n+\tif (!adev) {\n+\t\tdev_err(dev, \"failed to get associated PCIE-TGT device\\n\");\n+\t\treturn -ENODEV;\n+\t}\n+\n+\tINIT_LIST_HEAD(&resource_list);\n+\tret = acpi_dev_get_memory_resources(adev, &resource_list);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"failed to get PCIE-TGT device memory resources\\n\");\n+\t\tacpi_dev_put(adev);\n+\t\treturn ret;\n+\t}\n+\n+\trentry = list_first_entry_or_null(\n+\t\t&resource_list, struct resource_entry, node);\n+\tif (rentry) {\n+\t\tdata->addr_filter_reg = devm_ioremap_resource(dev, rentry->res);\n+\t\tret = 0;\n+\t}\n+\n+\tif (IS_ERR(data->addr_filter_reg)) {\n+\t\tdev_err(dev, \"failed to get address filter resource\\n\");\n+\t\tret = PTR_ERR(data->addr_filter_reg);\n+\t}\n+\n+\tacpi_dev_free_resource_list(&resource_list);\n+\tacpi_dev_put(adev);\n+\n+\tctx->data = data;\n+\n+\treturn ret;\n+}\n+#else\n+static int pcie_tgt_init_data(struct arm_cspmu *cspmu)\n+{\n+\treturn -ENODEV;\n+}\n+#endif\n+\n+static struct pcie_tgt_data *pcie_tgt_get_data(struct arm_cspmu *cspmu)\n+{\n+\tstruct nv_cspmu_ctx *ctx = to_nv_cspmu_ctx(cspmu);\n+\n+\treturn ctx->data;\n+}\n+\n+/* Find the first available address filter slot. */\n+static int pcie_tgt_find_addr_idx(struct arm_cspmu *cspmu, u64 base, u64 mask,\n+\tbool is_reset)\n+{\n+\tint i;\n+\tstruct pcie_tgt_data *data = pcie_tgt_get_data(cspmu);\n+\n+\tfor (i = 0; i < NV_PCIE_TGT_ADDR_COUNT; i++) {\n+\t\tif (!is_reset && data->addr_filter[i].refcount == 0)\n+\t\t\treturn i;\n+\n+\t\tif (data->addr_filter[i].base == base &&\n+\t\t\tdata->addr_filter[i].mask == mask)\n+\t\t\treturn i;\n+\t}\n+\n+\treturn -ENODEV;\n+}\n+\n+static u32 pcie_tgt_pmu_event_filter(const struct perf_event *event)\n+{\n+\tu32 filter;\n+\n+\tfilter = (event->attr.config >> NV_PCIE_TGT_EV_TYPE_COUNT) &\n+\t\tNV_PCIE_TGT_FILTER2_MASK;\n+\n+\treturn filter;\n+}\n+\n+static bool pcie_tgt_pmu_addr_en(const struct perf_event *event)\n+{\n+\tu32 filter = pcie_tgt_pmu_event_filter(event);\n+\n+\treturn FIELD_GET(NV_PCIE_TGT_FILTER2_ADDR_EN, filter) != 0;\n+}\n+\n+static u32 pcie_tgt_pmu_port_filter(const struct perf_event *event)\n+{\n+\tu32 filter = pcie_tgt_pmu_event_filter(event);\n+\n+\treturn FIELD_GET(NV_PCIE_TGT_FILTER2_PORT, filter);\n+}\n+\n+static u64 pcie_tgt_pmu_dst_addr_base(const struct perf_event *event)\n+{\n+\treturn event->attr.config1;\n+}\n+\n+static u64 pcie_tgt_pmu_dst_addr_mask(const struct perf_event *event)\n+{\n+\treturn event->attr.config2;\n+}\n+\n+static int pcie_tgt_pmu_validate_event(struct arm_cspmu *cspmu,\n+\t\t\t\t struct perf_event *new_ev)\n+{\n+\tu64 base, mask;\n+\tint idx;\n+\n+\tif (!pcie_tgt_pmu_addr_en(new_ev))\n+\t\treturn 0;\n+\n+\t/* Make sure there is a slot available for the address filter. */\n+\tbase = pcie_tgt_pmu_dst_addr_base(new_ev);\n+\tmask = pcie_tgt_pmu_dst_addr_mask(new_ev);\n+\tidx = pcie_tgt_find_addr_idx(cspmu, base, mask, false);\n+\tif (idx < 0)\n+\t\treturn -EINVAL;\n+\n+\treturn 0;\n+}\n+\n+static void pcie_tgt_pmu_config_addr_filter(struct arm_cspmu *cspmu,\n+\tbool en, u64 base, u64 mask, int idx)\n+{\n+\tstruct pcie_tgt_data *data;\n+\tstruct pcie_tgt_addr_filter *filter;\n+\tvoid __iomem *filter_reg;\n+\n+\tdata = pcie_tgt_get_data(cspmu);\n+\tfilter = &data->addr_filter[idx];\n+\tfilter_reg = data->addr_filter_reg + (idx * NV_PCIE_TGT_ADDR_STRIDE);\n+\n+\tif (en) {\n+\t\tfilter->refcount++;\n+\t\tif (filter->refcount == 1) {\n+\t\t\tfilter->base = base;\n+\t\t\tfilter->mask = mask;\n+\n+\t\t\twritel(lower_32_bits(base), filter_reg + NV_PCIE_TGT_ADDR_BASE_LO);\n+\t\t\twritel(upper_32_bits(base), filter_reg + NV_PCIE_TGT_ADDR_BASE_HI);\n+\t\t\twritel(lower_32_bits(mask), filter_reg + NV_PCIE_TGT_ADDR_MASK_LO);\n+\t\t\twritel(upper_32_bits(mask), filter_reg + NV_PCIE_TGT_ADDR_MASK_HI);\n+\t\t\twritel(1, filter_reg + NV_PCIE_TGT_ADDR_CTRL);\n+\t\t}\n+\t} else {\n+\t\tfilter->refcount--;\n+\t\tif (filter->refcount == 0) {\n+\t\t\twritel(0, filter_reg + NV_PCIE_TGT_ADDR_CTRL);\n+\t\t\twritel(0, filter_reg + NV_PCIE_TGT_ADDR_BASE_LO);\n+\t\t\twritel(0, filter_reg + NV_PCIE_TGT_ADDR_BASE_HI);\n+\t\t\twritel(0, filter_reg + NV_PCIE_TGT_ADDR_MASK_LO);\n+\t\t\twritel(0, filter_reg + NV_PCIE_TGT_ADDR_MASK_HI);\n+\n+\t\t\tfilter->base = 0;\n+\t\t\tfilter->mask = 0;\n+\t\t}\n+\t}\n+}\n+\n+static void pcie_tgt_pmu_set_ev_filter(struct arm_cspmu *cspmu,\n+\t\t\t\tconst struct perf_event *event)\n+{\n+\tbool addr_filter_en;\n+\tint idx;\n+\tu32 filter2_val, filter2_offset, port_filter;\n+\tu64 base, mask;\n+\n+\tfilter2_val = 0;\n+\tfilter2_offset = PMEVFILT2R + (4 * event->hw.idx);\n+\n+\taddr_filter_en = pcie_tgt_pmu_addr_en(event);\n+\tif (addr_filter_en) {\n+\t\tbase = pcie_tgt_pmu_dst_addr_base(event);\n+\t\tmask = pcie_tgt_pmu_dst_addr_mask(event);\n+\t\tidx = pcie_tgt_find_addr_idx(cspmu, base, mask, false);\n+\n+\t\tif (idx < 0) {\n+\t\t\tdev_err(cspmu->dev,\n+\t\t\t\t\"Unable to find a slot for address filtering\\n\");\n+\t\t\twritel(0, cspmu->base0 + filter2_offset);\n+\t\t\treturn;\n+\t\t}\n+\n+\t\t/* Configure address range filter registers.*/\n+\t\tpcie_tgt_pmu_config_addr_filter(cspmu, true, base, mask, idx);\n+\n+\t\t/* Config the counter to use the selected address filter slot. */\n+\t\tfilter2_val |= FIELD_PREP(NV_PCIE_TGT_FILTER2_ADDR, 1U << idx);\n+\t}\n+\n+\tport_filter = pcie_tgt_pmu_port_filter(event);\n+\n+\t/* Monitor all ports if no filter is selected. */\n+\tif (!addr_filter_en && port_filter == 0)\n+\t\tport_filter = NV_PCIE_TGT_FILTER2_PORT;\n+\n+\tfilter2_val |= FIELD_PREP(NV_PCIE_TGT_FILTER2_PORT, port_filter);\n+\n+\twritel(filter2_val, cspmu->base0 + filter2_offset);\n+}\n+\n+static void pcie_tgt_pmu_reset_ev_filter(struct arm_cspmu *cspmu,\n+\t\t\t\t const struct perf_event *event)\n+{\n+\tbool addr_filter_en;\n+\tu64 base, mask;\n+\tint idx;\n+\n+\taddr_filter_en = pcie_tgt_pmu_addr_en(event);\n+\tif (!addr_filter_en)\n+\t\treturn;\n+\n+\tbase = pcie_tgt_pmu_dst_addr_base(event);\n+\tmask = pcie_tgt_pmu_dst_addr_mask(event);\n+\tidx = pcie_tgt_find_addr_idx(cspmu, base, mask, true);\n+\n+\tif (idx < 0) {\n+\t\tdev_err(cspmu->dev,\n+\t\t\t\"Unable to find the address filter slot to reset\\n\");\n+\t\treturn;\n+\t}\n+\n+\tpcie_tgt_pmu_config_addr_filter(cspmu, false, base, mask, idx);\n+}\n+\n+static u32 pcie_tgt_pmu_event_type(const struct perf_event *event)\n+{\n+\treturn event->attr.config & NV_PCIE_TGT_EV_TYPE_MASK;\n+}\n+\n+static bool pcie_tgt_pmu_is_cycle_counter_event(const struct perf_event *event)\n+{\n+\tu32 event_type = pcie_tgt_pmu_event_type(event);\n+\n+\treturn event_type == NV_PCIE_TGT_EV_TYPE_CC;\n+}\n+\n enum nv_cspmu_name_fmt {\n \tNAME_FMT_GENERIC,\n \tNAME_FMT_SOCKET,\n@@ -622,6 +919,30 @@ static const struct nv_cspmu_match nv_cspmu_match[] = {\n \t\t.reset_ev_filter = nv_cspmu_reset_ev_filter,\n \t }\n \t},\n+\t{\n+\t .prodid = 0x10700000,\n+\t .prodid_mask = NV_PRODID_MASK,\n+\t .name_pattern = \"nvidia_pcie_tgt_pmu_%u_rc_%u\",\n+\t .name_fmt = NAME_FMT_SOCKET_INST,\n+\t .template_ctx = {\n+\t\t.event_attr = pcie_tgt_pmu_event_attrs,\n+\t\t.format_attr = pcie_tgt_pmu_format_attrs,\n+\t\t.filter_mask = 0x0,\n+\t\t.filter_default_val = 0x0,\n+\t\t.filter2_mask = NV_PCIE_TGT_FILTER2_MASK,\n+\t\t.filter2_default_val = NV_PCIE_TGT_FILTER2_DEFAULT,\n+\t\t.get_filter = NULL,\n+\t\t.get_filter2 = NULL,\n+\t\t.init_data = pcie_tgt_init_data\n+\t },\n+\t .ops = {\n+\t\t.is_cycle_counter_event = pcie_tgt_pmu_is_cycle_counter_event,\n+\t\t.event_type = pcie_tgt_pmu_event_type,\n+\t\t.validate_event = pcie_tgt_pmu_validate_event,\n+\t\t.set_ev_filter = pcie_tgt_pmu_set_ev_filter,\n+\t\t.reset_ev_filter = pcie_tgt_pmu_reset_ev_filter,\n+\t }\n+\t},\n \t{\n \t .prodid = 0,\n \t .prodid_mask = 0,\n@@ -714,6 +1035,8 @@ static int nv_cspmu_init_ops(struct arm_cspmu *cspmu)\n \n \t/* NVIDIA specific callbacks. */\n \tSET_OP(validate_event, impl_ops, match, NULL);\n+\tSET_OP(event_type, impl_ops, match, NULL);\n+\tSET_OP(is_cycle_counter_event, impl_ops, match, NULL);\n \tSET_OP(set_cc_filter, impl_ops, match, nv_cspmu_set_cc_filter);\n \tSET_OP(set_ev_filter, impl_ops, match, nv_cspmu_set_ev_filter);\n \tSET_OP(reset_ev_filter, impl_ops, match, NULL);\n", "prefixes": [ "v2", "5/8" ] }